ePlace-3D: Electrostatics based Placement for 3D-ICs

We propose a flat, analytic, mixed-size placement algorithm ePlace-3D for three-dimension integrated circuits (3D-ICs) using nonlinear optimization. Our contributions are (1) electrostatics based 3D density function with globally uniform smoothness (2) 3D numerical solution with improved spectral formulation (3) 3D nonlinear pre-conditioner for convergence acceleration (4) interleaved 2D-3D placement for efficiency enhancement. Our placer outperforms the leading work mPL6-3D and NTUplace3-3D with 6.44% and 37.15% shorter wirelength, 9.11% and 10.27% fewer 3D vertical interconnects (VI) on average of IBM-PLACE circuits. Validation on the large-scale modern mixed-size (MMS) 3D circuits shows high performance and scalability.

[1]  Jason Cong,et al.  An Analytical Placement Framework for 3-D ICs and Its Extension on Thermal Awareness , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Jin Hu,et al.  Progress and Challenges in VLSI Placement Research , 2012, Proceedings of the IEEE.

[3]  Yao-Wen Chang,et al.  Routability-driven analytical placement for mixed-size circuit designs , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[4]  Chung-Kuan Cheng,et al.  Performance-driven placement for design of rotation and right arithmetic shifters in monolithic 3D ICs , 2013, 2013 International Conference on Communications, Circuits and Systems (ICCCAS).

[5]  Joseph R. Shinnerl,et al.  mPL6: enhanced multilevel mixed-size placement , 2006, ISPD '06.

[6]  Wing-Kai Chow,et al.  A new clock network synthesizer for modern VLSI designs , 2012, Integr..

[7]  Gunilla Sköllermo.  A Fourier method for the numerical solution of Poisson's equation , 1975 .

[8]  Wing-Kai Chow,et al.  Fast Power- and Slew-Aware Gated Clock Tree Synthesis , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  Andrew B. Kahng,et al.  A faster implementation of APlace , 2006, ISPD '06.

[10]  Chris C. N. Chu,et al.  Handling complexities in modern large-scale mixed-size placement , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[11]  David Lee,et al.  Detecting job interference in large distributed multi-agent systems — A formal approach , 2013, 2013 IFIP/IEEE International Symposium on Integrated Network Management (IM 2013).

[12]  Igor L. Markov,et al.  ComPLx: A competitive primal-dual Lagrange optimization for global placement , 2012, DAC Design Automation Conference 2012.

[13]  Evangeline F. Y. Young,et al.  Congestion prediction in early stages of physical design , 2009, TODE.

[14]  Chris C. N. Chu,et al.  An efficient and effective detailed placement algorithm , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[15]  Frank M. Johannes,et al.  Generic global placement and floorplanning , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[16]  Wing-Kai Chow,et al.  Clock Network Synthesis with Concurrent Gate Insertion , 2010, PATMOS.

[17]  Yao-Wen Chang,et al.  Unified analytical global placement for large-scale mixed-size circuit designs , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[18]  Jingwei Lu.  Analytic VLSI Placement using Electrostatic Analogy , 2014 .

[19]  B. Ripley,et al.  Robust Statistics , 2018, Encyclopedia of Mathematical Geosciences.

[20]  Sachin S. Sapatnekar,et al.  Placement of 3D ICs with Thermal and Interlayer Via Considerations , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[21]  Chin-Long Wey,et al.  Reliable Power Delivery System Design for Three-Dimensional Integrated Circuits (3D ICs) , 2012, 2012 IEEE Computer Society Annual Symposium on VLSI.

[22]  Duo Chen,et al.  From Layout Directly to Simulation: A First-Principle-Guided Circuit Simulator of Linear Complexity and Its Efficient Parallelization , 2012, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[23]  Gi-Joon Nam,et al.  ISPD 2006 Placement Contest: Benchmark Suite and Results , 2006, ISPD '06.

[24]  Ulf Schlichtmann,et al.  Kraftwerk2—A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[25]  Yao-Wen Chang,et al.  NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[26]  Andreas Gerstlauer,et al.  Approximate logic synthesis under general error magnitude and frequency constraints , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[27]  Evangeline F. Y. Young,et al.  A dual-MST approach for clock network synthesis , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

[28]  Chung-Kuan Cheng,et al.  ePlace: Electrostatics based placement using Nesterov's method , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[29]  Hong Wang,et al.  How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core , 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

[30]  Andrew B. Kahng,et al.  Stability and scalability in global routing , 2011, International Workshop on System Level Interconnect Prediction.

[31]  Jason Cong,et al.  Thermal-Aware 3D IC Placement Via Transformation , 2007, 2007 Asia and South Pacific Design Automation Conference.

[32]  Tao Wang,et al.  Critical path monitor enabled dynamic voltage scaling for graceful degradation in sub-threshold designs , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[33]  Tao Wang,et al.  Eagle-Eye: A near-optimal statistical framework for noise sensor placement , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[34]  C. D. Gelatt,et al.  Optimization by Simulated Annealing , 1983, Science.

[35]  Andreas Gerstlauer,et al.  Multi-level approximate logic synthesis under general error constraints , 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[36]  Ku He,et al.  Modeling and synthesis of quality-energy optimal approximate adders , 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[37]  Sung Kyu Lim,et al.  Study of Through-Silicon-Via Impact on the 3-D Stacked IC Layout , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[38]  Sung Kyu Lim,et al.  A study of Through-Silicon-Via impact on the 3D stacked IC layout , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[39]  Gi-Joon Nam,et al.  The ISPD2005 placement contest and benchmark suite , 2005, ISPD '05.

[40]  Dongjin Lee,et al.  SimPL: An effective placement algorithm , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[41]  Chiu-Wing Sham,et al.  LMgr: A low-M emory global router with dynamic topology update and bending-aware optimum path search , 2013, International Symposium on Quality Electronic Design (ISQED).

[42]  Chung-Kuan Cheng,et al.  ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[43]  Yao-Wen Chang,et al.  TSV-Aware Analytical Placement for 3-D IC Designs Based on a Novel Weighted-Average Wirelength Model , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[44]  Yao-Wen Chang,et al.  Unified analytical global placement for large-scale mixed-size circuit designs , 2010, ICCAD 2010.

[45]  Yang Liu,et al.  Worst-Case Noise Area Prediction of On-Chip Power Distribution Network , 2014, SLIP 2014.

[46]  Y. Nesterov.  A method for solving the convex programming problem with convergence rate O(1/k^2) , 1983 .

[47]  Chung-Kuan Cheng,et al.  ePlace: Electrostatics-Based Placement Using Fast Fourier Transform and Nesterov's Method , 2015, TODE.

[48]  Sachin Sapatnekar,et al.  Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach , 2003, ICCAD 2003.

[49]  Chris C. N. Chu,et al.  FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control , 2007, 2007 Asia and South Pacific Design Automation Conference.

[50]  Peter J. Huber,et al.  Robust Statistics , 2005, Wiley Series in Probability and Statistics.

[51]  Jingwei Lu,et al.  Fundamental Research on Electronic Design Automation in VLSI Design - Routability , 2010 .

[52]  Chung-Kuan Cheng,et al.  FFTPL: An analytic placement algorithm using fast fourier transform for density equalization , 2013, 2013 IEEE 10th International Conference on ASIC.