论文信息 - Analysis and modeling of four-folded vertical Hall devices in current domain

Analysis and modeling of four-folded vertical Hall devices in current domain

This paper presents a four-folded current-mode vertical Hall device. The current spinning technique is applied to a vertical Hall sensor driven in current mode to eliminate the offset and to increase the sensitivity. Different geometries have been studied and simulated by using a simulator based on finite element method. A four-folded three contacts vertical Hall device model displayed the lowest residual offset and the best sensitivity. Simulations results, obtained in two different environments, are compared and discussed. COMSOL results are validated with respect to the electrical behavior of an 8-resistor Verilog-A model implemented in Cadence environment. Simulations show that the achieved sensitivity can be better than 160 mT-1, a remarkable performance for vertical Hall sensors.

[1] Enrico Schurig,et al. Highly sensitive vertical hall sensors in CMOS technology , 2005 .

[2] Mirjana Banjevic,et al. High Bandwidth CMOS Magnetic Sensors Based on the Miniaturized Circular Vertical Hall Device , 2011 .

[3] Oliver Paul,et al. Analysis of the offset of semiconductor vertical Hall devices , 2012 .

[4] Patrick Ruther,et al. A computationally efficient numerical model of the offset of CMOS-integrated vertical Hall devices , 2012 .

[5] M. Cornils,et al. Fully symmetric vertical hall devices in CMOS technology , 2013, 2013 IEEE SENSORS.

[6] Guo-Ming Sung,et al. 2-D Differential Folded Vertical Hall Device Fabricated on a P-Type Substrate Using CMOS Technology , 2013, IEEE Sensors Journal.

[7] Hadi Heidari,et al. Low-noise low-Offset current-mode Hall sensors , 2013, Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME).