A framework for performance-based program partitioning

Most of the reported work in the Parallelizing Compilers literature focuses on analyzing program characteristics such as the dependencies, loop structures, memory reference patterns etc. to optimize the generated parallel code [3, 2, 7, 8, 14, 10]. Unfortunately, parallelizing compilers have very little or no knowledge of the actual run time behavior of the synthesized code on the underlying hardware due to the complex behavior of the underlaying hardware and software subsystems. This interaction could significantly affect the performance of the generated code and must be considered during program partitioning phases of the compiler. In this paper, we present an efficient and accurate performance model based program partitioning approach for parallel architectures. We introduce the concept of behavioral edges for capturing the interactions between computation and communication through parametric functions. We present an efficient algorithm to identify behavioral edges, modify costs using the behavioral edges and adapt the schedule to improve schedule length. The program partitioning phase uses the static estimates computed using the behavioral edges and partitioning is iteratively performed using the ordering PDG based on computed intervals. A significant performance improvement (factor of 10 in many cases) is demonstrated by using our framework.