Realistic fault extraction for high-quality design and test of VLSI systems

The purpose of this paper is to present a methodology for circuit and realistic fault extraction, and its implementation in a new tool, lobs, to be included in a virtual test environment, DOTLab. Digital, analog and mixed signal ICs, implemented in CMOS, bipolar or BiCMOS technologies are handled both in Manhattan and 45/spl deg/ geometries. Higher level design data, obtained in the top-down design flow, is used for realistic fault characterization. A sliding window algorithm is extended for fault extraction of non-orthogonal geometries. An accurate critical area evaluation algorithm is proposed to compute the probability of occurrence of the defects. Over 100,000 transistor ICs are analyzed for bridging defects.

[1]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[2]  William E. Lorensen,et al.  Object-Oriented Modeling and Design , 1991, TOOLS.

[3]  João Paulo Teixeira,et al.  Defect-oriented IC test and diagnosis using VHDL fault simulation , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[4]  John Paul Shen,et al.  Extraction and simulation of realistic CMOS faults using inductive fault analysis , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[5]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[6]  João Paulo Teixeira,et al.  Integrated approach for circuit and fault extraction of VLSI circuits , 1996, Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[7]  A. V. Ferris-Prabhu,et al.  Defect size variations and their effect on the critical area of VLSI devices , 1985 .

[8]  Peter C. Maxwell,et al.  The Effectiveness of IDDQ, Functional and Scan Tests: How Many Fault Coverages Do We Need? , 1992, ITC.

[9]  J. Pineda de Gyvez.  IC defect-sensitivity : theory and computational models for yield prediction , 1991 .

[10]  Tracy Larrabee,et al.  Testing CMOS logic gates for: realistic shorts , 1994, Proceedings., International Test Conference.

[11]  Charles H. Stapper,et al.  Modeling of Integrated Circuit Defect Sensitivities , 1983, IBM J. Res. Dev..

[12]  J. Pineda de Gyvez,et al.  IC defect sensitivity for footprint-type spot defects , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  João Paulo Teixeira,et al.  Physical design of testable CMOS digital integrated circuits , 1991 .

[14]  João Paulo Teixeira,et al.  Test preparation for high coverage of physical defects in CMOS digital ICs , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[15]  Marcel Jacomet,et al.  Fantestic: towards a powerful fault analysis and test pattern generator for integrated circuits , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[16]  Grady Booch,et al.  Object-Oriented Design with Applications , 1990 .

[17]  João Paulo Teixeira,et al.  Defect level evaluation in an IC design environment , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  M. Ray Mercer,et al.  On the decline of testing efficiency as fault coverage approaches 100% , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[19]  John Paul Shen,et al.  Inductive Fault Analysis of MOS Integrated Circuits , 1985, IEEE Design & Test of Computers.

[20]  F. Joel Ferguson,et al.  Sandia National Labs , 2022 .

[21]  Jag Sodhi,et al.  Object-oriented methods for software development , 1996 .

[22]  Wojciech Maly,et al.  Layout-driven test generation , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.