Low power architectures using localised non-volatile memory and selective power shut-down

A method and associated circuit and architectural implementations to reduce the power dissipation for the digital part of a system-on-a-chip (SOC) while maintaining the overall system performances (such as speed) unaffected are described. An alternative application is to provide fast recovery from a power shut-down event up to the level of instruction (or clock cycle) execution

[1]  J. Slaughter,et al.  Progress and outlook for MRAM technology , 1999, IEEE International Magnetics Conference.

[2]  Eby G. Friedman,et al.  A dynamic reconfigurable clock generator , 2001, Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558).

[3]  Jan M. Rabaey,et al.  Hybrid reconfigurable processors-the road to low-power consumption , 1998, Proceedings Eleventh International Conference on VLSI Design.

[4]  Juanjo Noguera,et al.  HW/SW codesign techniques for dynamically reconfigurable architectures , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[5]  Kaushik Roy,et al.  Reducing leakage in a high-performance deep-submicron instruction cache , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[6]  A. Veidenbaum,et al.  Architectural and compiler strategies for dynamic power management in the COPPER project , 2001, 2001 Innovative Architecture for Future Generation High-Performance Processors and Systems.