A fully symmetrical sense amplifier for non-volatile memories

This paper presents a fully symmetrical sense amplifier topology for advanced non-volatile memories. The proposed structure ensures zero systematic offset, together with adequate rejection of disturbs coming from capacitive coupling with noisy substrate, power supply, and ground. The presented topology has been designed for phase change memories, however, it is also suitable for use in other non-volatile storage devices such as magnetic RAMs and Flash memories. Experimental results on sensing time, offset, and sensitivity demonstrated the effectiveness of the proposed scheme.

[1]  Guy C. Wicker.  Nonvolatile high-density high-performance phase-change memory , 1999, Smart Materials, Nano-, and Micro- Smart Systems.

[2]  Peter Stubberud,et al.  CMOS current mode flash analog to digital converter , 2001, Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257).

[3]  A.A.M. Amin.  Design and analysis of a high-speed sense amplifier for single-transistor nonvolatile memory cells , 1993 .

[4]  G. Torelli,et al.  An improved method for programming a word-erasable EEPROM , 1983 .

[5]  T. Lowrey,et al.  Ovonic unified memory - a high-performance nonvolatile memory technology for stand-alone memory and embedded applications , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[6]  Greg Atwood,et al.  A multilevel-cell 32 Mb flash memory , 2000, Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000).

[7]  L. Heller,et al.  Cascode voltage switch logic: A differential CMOS logic family , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[8]  M. Dallabora,et al.  A 1mb Cmos Eprom With Enhanced Verification , 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.

[9]  M. Durlam,et al.  Nonvolatile RAM based on magnetic tunnel junction elements , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[10]  B. Vajdic,et al.  A 90-ns one-million erase/program cycle 1-Mbit flash memory , 1989 .