Delay modelling improvement for low voltage applications

Based on an explicit formulation of delays, an improved model for low voltage operation of CMOS inverter has been derived. Extrinsic and intrinsic effects, such as transistor current variation, input slew rate effects and mobility improvement at low field are considered. Explicit dependence of inverter delay on input controlling ramp is given with clear evidence of supply and threshold voltage influences. Validations are obtained by comparing the calculated and measured oscillation period evolution of ring oscillators, under supply voltage conditions varying from standard 5/spl nu/, to values as low as the highest threshold voltage of the process involved. The speed performance evolution and the limits to the reduction of supply voltage are clearly given in terms of threshold voltage values.

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