3DBUFFBLESS: A novel buffered-bufferless hybrid router for 3D Networks-on-Chip

This paper presents the design, simulation implementation and evaluation of a novel 3D NoC router that combines buffered and bufferless routing. Our proposal is an asymmetrical router that is buffered in the z dimension and bufferless in the x- and y dimensions. Experimental results show that the proposed router effectively combines the advantages of both buffered and bufferless routers. Compared to baseline buffered-only and bufferless-only routers, by achieving higher routing efficiency and significantly higher performance than state-of-the-art bufferless routers, while maintaining low area and power consumption. According to the experimental results, the proposed router performance degrades more gracefully than a bufferless router's. More specifically, the proposed router achieves a latency improvement of 10–20% below the network saturation point (the traffic load value above which network performance degrades significantly) and 44–48% above, compared to 3D bufferless routers proposed in the literature, when prototyped in FPGA technology.