Analytical current equation for short channel SOI multigate FETs including 3D effects

Current flow in short-channel multigate FETs is strongly influenced by 2D or even 3D effects. In subthreshold operation the channel current is located in the device center, whereas above threshold the channel moves to the silicon-to-oxide interface. This movement of the most leaky path can result in an abnormal behavior in the transconductance. In this paper an analytical current equation for lightly doped devices is proposed which takes into account these effects. The leakage current is calculated from a three-dimensional solution of the electrostatic potential at the barrier within the channel. For the current above threshold, which is located at the channel surface, a bulk MOS model is superposed. The final current equation takes into account short-channel effects as threshold voltage shift, drain-induced barrier lowering, subthreshold slope degradation and the movement of the most leaky path within the channel cross section. The model has been benchmarked by numerical results and is in good agreement down to a channel length of 30 nm.

[1]  C.C. McAndrew,et al.  Validation of MOSFET model Source–Drain Symmetry , 2006, IEEE Transactions on Electron Devices.

[2]  Ernst Weber,et al.  Electromagnetic fields , 1950 .

[3]  J.J. Liou,et al.  A Review of Core Compact Models for Undoped Double-Gate SOI MOSFETs , 2007, IEEE Transactions on Electron Devices.

[4]  N. Arora.  MOSFET Models for VLSI Circuit Simulation , 1993 .

[5]  R. Rooyackers,et al.  Multi-gate devices for the 32nm technology node and beyond , 2007, ESSDERC 2007 - 37th European Solid State Device Research Conference.

[6]  Alexander Kloes,et al.  Unified current equation for predictive modeling of submicron MOSFETs , 2005 .

[7]  Y. Taur,et al.  A continuous, analytic drain-current model for DG MOSFETs , 2004 .

[8]  A. Kloes,et al.  Three-Dimensional Closed-Form Model for Potential Barrier in Undoped FinFETs Resulting in Analytical Equations for $V_{T}$ and Subthreshold Slope , 2008, IEEE Transactions on Electron Devices.

[9]  A. Kostka,et al.  A new analytical method of solving 2D Poisson's equation in MOS devices applied to threshold voltage and subthreshold modeling , 1996 .

[10]  G. Pei,et al.  FinFET design considerations based on 3-D simulation and analytical modeling , 2002 .

[11]  B. Iñíguez,et al.  2D physics-based compact model for channel length modulation in lightly doped DG FETs , 2009, 2009 MIXDES-16th International Conference Mixed Design of Integrated Circuits & Systems.

[12]  S. Hareland,et al.  Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout , 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

[13]  F. Danneville,et al.  Compact-Modeling Solutions For Nanoscale Double-Gate and Gate-All-Around MOSFETs , 2006, IEEE Transactions on Electron Devices.

[14]  Alexander Kloes,et al.  Analysis of 3D current flow in undoped FinFETs and approaches for compact modeling , 2009, 2009 MIXDES-16th International Conference Mixed Design of Integrated Circuits & Systems.

[15]  B. Iniguez,et al.  Precise Modeling Framework for Short-Channel Double-Gate and Gate-All-Around MOSFETs , 2008, IEEE Transactions on Electron Devices.

[16]  H. A. Hamid,et al.  Explicit continuous model for long-channel undoped surrounding gate MOSFETs , 2005, IEEE Transactions on Electron Devices.