A Reliable Nano Device with Appropriate Performance in High Temperatures

[1]  H. Tango,et al.  Two-dimensional simulation and measurement of high-performance MOSFETs made on a very thin SOI film , 1989 .

[2]  A. Orouji,et al.  Double step buried oxide (DSBO) SOI-MOSFET: A proposed structure for improving self-heating effects , 2009 .

[3]  Ali Afzali-Kusha,et al.  Ground plane fin-shaped field effect transistor (GP-FinFET): A FinFET for low leakage power circuits , 2012 .

[4]  Bo Zhang,et al.  Low on-Resistance SOI Dual-Trench-Gate MOSFET , 2012, IEEE Transactions on Electron Devices.

[5]  Controlling floating body effect in high temperatures: L-shape SiGe region in nano-scale MOSFET , 2015 .

[6]  A. A. Kusha,et al.  Process variation study of Ground Plane SOI MOSFET , 2010, 2nd Asia Symposium on Quality Electronic Design (ASQED).

[7]  S. K. Sarkar,et al.  Spatial Composition Grading of Binary Metal Alloy Gate Electrode for Short-Channel SOI/SON MOSFET Application , 2012, IEEE Transactions on Electron Devices.

[8]  J. Colinge.  Silicon-on-Insulator Technology: Materials to VLSI , 1991 .

[9]  Liu Yongchang,et al.  A high-voltage SOI MOSFET with a compensation layer on the trenched buried oxide layer , 2013 .

[10]  Ru Huang,et al.  Scaling of lowered source/drain (LSD) and raised source/drain (RSD) ultra-thin body (UTB) SOI MOSFETs , 2005 .

[11]  A. Naderi.  Double gate graphene nanoribbon field effect transistor with single halo pocket in channel region , 2016 .

[12]  A. Orouji,et al.  A new nanoscale and high temperature field effect transistor: Bi level FinFET , 2011 .

[14]  S. Selberherr.  Analysis and simulation of semiconductor devices , 1984 .

[15]  Vala Fathipour,et al.  The Impact of Process Parameters on the Output Characteristics of an LDMOS Device , 2010 .

[16]  Wen-Yan Yin,et al.  Electrothermal Effects on Hot-Carrier Reliability in SOI MOSFETs—AC Versus Circuit-Speed Random Stress , 2016, IEEE Transactions on Electron Devices.

[17]  S. E. J. Mahabadi.  Upper drift region double step partial SOI LDMOSFET: A novel device for enhancing breakdown voltage and output characteristics , 2016 .

[18]  M. Zareiee,et al.  A novel high performance nano-scale MOSFET by inserting Si3N4 layer in the channel , 2015 .

[19]  S. Cristoloveanu,et al.  Mobility Enhancement by Back-Gate Biasing in Ultrathin SOI MOSFETs With Thin BOX , 2012, IEEE Electron Device Letters.

[20]  C. Qiu,et al.  A Tunnel Diode Body Contact Structure for High-Performance SOI MOSFETs , 2012, IEEE Transactions on Electron Devices.

[21]  Experimental study on quantum mechanical effect for insensitivity of threshold voltage against temperature variation in strained SOI MOSFETs , 2015, 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

[22]  Sorin Cristoloveanu,et al.  Silicon on insulator technologies and devices: from present to future , 2001 .

[23]  A. Orouji,et al.  A novel high breakdown voltage LDMOS by protruded silicon dioxide at the drift region , 2016 .

[24]  A. Orouji,et al.  Partially Cylindrical Fin Field-Effect Transistor: A Novel Device for Nanoscale Applications , 2010, IEEE Transactions on Device and Materials Reliability.

[25]  S. Sarkar,et al.  Work Function Engineering With Linearly Graded Binary Metal Alloy Gate Electrode for Short-Channel SOI MOSFET , 2012, IEEE Transactions on Nanotechnology.

[26]  Yuan Taur,et al.  Comprehensive Analysis of Short-Channel Effects in Ultrathin SOI MOSFETs , 2013, IEEE Transactions on Electron Devices.