Avalanche: an environment for design space exploration and optimization of low-power embedded systems

We present Avalanche, a prototyping framework that addresses the issues of power estimation and optimization for mixed hardware and software embedded systems. Avalanche is based on a generic embedded system architecture consisting of embedded CPU, custom hardware, and a memory hierarchy. For system-level power estimation, given various system parameters like cache sizes, cache policies, and bus width, etc., Avalanche is able to rapidly evaluate/estimate power and performance and thus facilitate comprehensive design space explorations. For system-level power optimization, Avalanche offers different modes reflecting various design scenarios: if no hardware/software partitioning or only partial partitioning has been conducted, Avalanche guides the designer in finding power-aware hardware/software partitioning; when a system has already been partitioned, Avalanche can optimize system parameters such as cache and memory size; if system parameters and partitioning are given, Avalanche applies additional optimizations for power including source-to-source compiler transformations. Avalanche has been deployed during the design phase of real-world applications including an MPEG II encoder in a set-top box design. Extensive design space explorations in terms of power and performance could be conducted within several hours and various optimization techniques led to power reductions of up to 94% without performance losses and only a slight increases in total chip size (i.e., transistor count).

[1]  Miodrag Potkonjak,et al.  Power optimization of variable-voltage core-based systems , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  G. De Micheli,et al.  Cycle-accurate simulation of energy consumption in embedded systems , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[3]  Y. Nakagome,et al.  Trends in low-power RAM circuit technologies , 1995 .

[4]  K. Ghose,et al.  Analytical energy dissipation models for low power caches , 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.

[5]  S. Malik,et al.  Instruction level power analysis and optimization of software , 1996, Proceedings of 9th International Conference on VLSI Design.

[6]  Nikil D. Dutt,et al.  Architectural exploration and optimization of local memory in embedded systems , 1997, Proceedings. Tenth International Symposium on System Synthesis (Cat. No.97TB100114).

[7]  Jan M. Rabaey,et al.  Architectural power analysis: The dual bit type method , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[8]  Yervant Zorian,et al.  Introducing Core-Based System Design , 1997, IEEE Des. Test Comput..

[9]  Niraj K. Jha,et al.  COSYN: hardware-software co-synthesis of embedded systems , 1997, DAC.

[10]  Luca Benini,et al.  Synthesis of low-overhead interfaces for power-efficient communication over wide buses , 1999, DAC '99.

[11]  Toshinori Sato,et al.  Power and performance simulator: ESP and its application for 100 MIPS/W class RISC design , 1994, Proceedings of 1994 IEEE Symposium on Low Power Electronics.

[12]  Pierre Bricaud,et al.  Reuse methodology manual for system-on-chip designs , 1998 .

[13]  Jörg Henkel,et al.  Code compression for low power embedded system design , 2000, Proceedings 37th Design Automation Conference.

[14]  Alfred V. Aho,et al.  Compilers: Principles, Techniques, and Tools , 1986, Addison-Wesley series in computer science / World student series edition.

[15]  Niraj K. Jha,et al.  Power analysis of embedded operating systems , 2000, Proceedings 37th Design Automation Conference.

[16]  Mahmut T. Kandemir,et al.  Influence of compiler optimizations on system power , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[17]  Norman P. Jouppi,et al.  WRL Research Report 93/5: An Enhanced Access and Cycle Time Model for On-chip Caches , 1994 .

[18]  Jörg Henkel,et al.  An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[19]  Ping-Wen Ong,et al.  Power-conscious software design-a framework for modeling software on hardware , 1994, Proceedings of 1994 IEEE Symposium on Low Power Electronics.

[20]  Frank Vahid,et al.  A hybrid approach for core-based system-level power modeling , 2000, ASP-DAC '00.

[21]  Luciano Lavagno,et al.  Efficient power co-estimation techniques for system-on-chip design , 2000, DATE '00.

[22]  Luca Benini,et al.  Selective instruction compression for memory energy reduction in embedded systems , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[23]  Miodrag Potkonjak,et al.  Potential-driven statistical ordering of transformations , 1997, DAC.

[24]  Youngsoo Shin,et al.  Power conscious fixed priority scheduling for hard real-time systems , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[25]  Sharad Malik,et al.  Instruction level power analysis and optimization of software , 1996, J. VLSI Signal Process..

[26]  Cristina Silvano,et al.  Power estimation for architectural exploration of HW/SW communication on system-level buses , 1999, CODES '99.

[27]  Cheng-Ta Hsieh,et al.  Profile-driven Program Synthesis For Evaluation Of System Power Dissipation , 1997, Proceedings of the 34th Design Automation Conference.

[28]  Vivek Tiwari.  Logic and system design for low power consumption , 1996 .

[29]  M. Horowitz,et al.  Energy dissipation in general purpose processors , 1995, 1995 IEEE Symposium on Low Power Electronics. Digest of Technical Papers.

[30]  Miodrag Potkonjak,et al.  Power optimization of variable voltage core-based systems , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[31]  Jörg Henkel,et al.  Fast timing analysis for hardware-software co-synthesis , 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.