A Low-power Synthesizable Time-to-Digital Converter using Amplification to Overcome Mismatch

This paper presents a synthesizable cyclic vernier time to digital converter (TDC) based on ring oscillators. All circuits are automatically placed and routed without any custom layout or design. The mismatch in the circuits are eliminated by the proposed calibration circuit, which utilizes the effect that the amplified time signal can be much larger than the effect of wire parasitic, thus cancelling its own mismatch. The designed calibration circuit stops working during the conversion to save power consumption. To save areas, the counter circuit is re-used during the calibration and the conversion period by working alternatively. In addition, the throughput rate is optimized based on the proposed double-detector structure. The proposed TDC is designed with CMOS 130nm process by automatic placement and routing. The post layout simulation results show that it achieves 2.8ps resolution and consumes 0.47mW, which is the lowest-power synthesizable TDC reported so far to the author’s best knowledge. This work occupies only 0.0016mm2 layout area, which may be the smallest synthesizable TDC known at present if considering the scaling-down rule.

[1]  Taeik Kim,et al.  15.5 A 0.6V 1.17ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14nm FinFET technology , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[2]  Günhan Dündar,et al.  A synthesizable Time to Digital Converter (TDC) with MIMO spatial oversampling method , 2015, 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS).

[3]  Michiel Steyaert,et al.  A standard cell based all-digital Time-to-Digital Converter with reconfigurable resolution and on-line background calibration , 2011, 2011 Proceedings of the ESSCIRC (ESSCIRC).

[4]  N. Felber,et al.  A delay-line based DCO for multimedia applications using digital standard cells only , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[5]  Youngmin Park,et al.  A cyclic vernier time-to-digital converter synthesized from a 65nm CMOS standard library , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[6]  Youngmin Park,et al.  An all-digital PLL synthesized from a digital standard cell library in 65nm CMOS , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[7]  Youngmin Park,et al.  A Cyclic Vernier TDC for ADPLLs Synthesized From a Standard Cell Library , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[8]  Akira Matsuzawa,et al.  A 14-b, 850fs Fully Synthesizable Stochastic-Based Branching Time-to-Digital Converter in 65nm CMOS , 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

[9]  Xing Zhou,et al.  Low-Phase Noise Clock Distribution Network Using Rotary Traveling-Wave Oscillators and Built-In Self-Test Phase Tuning Technique , 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

[10]  Kenichi Okada,et al.  A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique , 2015, IEEE Journal of Solid-State Circuits.

[11]  Ulf Schlichtmann,et al.  Fully synthesized time-to-digital converter for cellular transceivers , 2016, 2016 Second International Conference on Event-based Control, Communication, and Signal Processing (EBCCSP).

[12]  David D. Wentzloff,et al.  A 0.009 mm2 Wide-Tuning Range Automatically Placed-and-Routed ADPLL in 14-nm FinFET CMOS , 2018, IEEE Solid-State Circuits Letters.