Parallelizing High-Level Synthesis: A Code Transformational Approach to High-Level Synthesis

Synthesis is the process of generating circuit implementations from descriptions of what a component does. Synthesis in part consists of refinement, elaboration as well as transformations and optimizations at multiple levels to generate circuits that compare favorably with manual designs. High-level synthesis (HLS) or behavioral synthesis specifically refers to circuit synthesis from algorithmic (or behavioral) descriptions. In this chapter, we focus on the developments in code transformation techniques for HLS over the past two decades, and describe recent progress in coordinated compiler and HLS transformations that seeks to combine effectively advances in parallelizing compiler techniques. We describe how coordinated compiler and HLS techniques can yield efficient circuits through examples of a class of source-level and dynamic transformations. We also describe recent developments in system-level modeling techniques and languages that attempt to raise the level of abstraction in the design process. 10-1 Gaurav Singh Virginia Tech Sumit Gupta Tensilica Inc. Sandeep Shukla Virginia Tech Rajesh Gupta UC, San Deigo CRC_7923_Ch010.qxd 11/15/2005 12:05 PM Page 1

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