Si interposers integrated with SrTiO3 thin film decoupling capacitors and through-Si-vias

Si interposers with SrTiO3 (STO) thin film capacitors and their stacking process based on chip-to-wafer bonding have been developed. To reduce defect density in chip-size capacitors, the STO thin films were sputter-deposited at 400degC, and Ru was used as a bottom electrode. The stacking process enables the 50-mum-thick Si interposers to be inserted between an LSI and a board. Maximum capacitance density of 2.5 muF/cm2 was obtained for 60-nm-thick STO capacitors in an area of 20 mm times 20 mm with 9000 through-silicon-vias (TSVs). Capacitance for the LSI/Si interposer stacks with 1 muF and 1600 TSVs did not change during a thermal cycle test up to 1000 cycles.