Compiler-based data classification for hybrid caching

As chip multiprocessor systems incorporate an increasing number of cores, memory access latency, impacted by on-chip communication and remote data cache access, is becoming a critical bottleneck. To combat the problem, advanced cache organizations have been proposed as alternatives to traditional private and static non-uniform cache access (e.g. distributed shared) architectures. In this paper, we demonstrate how using fairly simple compiler analysis memory accesses can be classified into private data access and shared data access. In addition, we introduce a third classification of probably private access and demonstrate the impact of this category compared to traditional private and shared. The memory access classification information from the compiler analysis is then provided to the runtime system through the page table to facilitate a hybrid private-shared caching technique. The proposed cache mechanism distinguishes data access patterns and adopts different placement and search policies accordingly to improve the performance. Our analysis demonstrates that many applications have a significant amount of both private and shared data and that compiler analysis can identify the private data effectively for many applications.