论文信息 - A 4.5 GHz 130 nm 32 KB L0 cache with a self reverse bias scheme

A 4.5 GHz 130 nm 32 KB L0 cache with a self reverse bias scheme

This paper describes a 32 KB dual-ported L0 cache for 4.5 GHz operation in 1.2 V, 130 nm CMOS. The local bitline uses a Self Reverse Bias scheme to achieve -220 mV access transistor underdrive without external bias voltage or gate-oxide overstress. 11% faster read delay and 104% higher DC robustness (including 7x measured active leakage reduction) is achieved over optimized high-performance dual-Vt scheme.

[1] M. Hussein,et al. A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).