Design Verification of an Embedded Processor: From Error Model to Test Method

This paper presents a new error model for itemmissing bugs, which are paid little attention by traditional error models. Such bugs do exist in practice, and are substantiated via our collection of bugs in a real project: a wireless sensor network oriented embedded processor. The test generation method for such error model is proposed, and is applied in verification of our design. Experimental results demonstrate that structural information got from this error model is helpful to reach a greater probability of bug detection than that in randomgeneration verification with only functional constraints.

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