Delay based Physical Unclonable Function for Hardware Security and Trust

Hardware security has become an important concern today. As the design passes on through many hands, there are chances that some malicious circuits can be introduced by the attackers. In addition, unauthorized people may try to access the IC and read or even change the information stored. To prevent accessing of device by unauthorized persons, Physical Unclonable Function (PUF) is invented. PUF, which has unique response for a given challenge, is a function which is easy to evaluate but not easy to replicate. Several PUF structures were proposed in literature for both ASIC and FPGA to improve the metrics, mainly uniqueness and uniformity. But the maximum uniqueness achieved by these structures is 40%. In this paper, we present a strong PUF which produces several Challenge Response Pairs (CRPs) and also improves uniqueness. This PUF structure is a combination of Flip Flop based Arbiter PUF (FF APUF) and XOR PUF. This PUF is implemented on Virtex 6, Spartan 6 and Spartan 3 FPGAs and its uniqueness is evaluated and is compared with that of FF APUF. Our XOR FF APUF gives uniqueness of 46% on Virtex 6, 43% on Spartan 3 and 48% on Spartan 6 boards which is higher than that of FF APUF by 14%, 16% and 7% respectively.

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