Ground noise minimization in integrated circuit packages through pin assignment optimization

Due to suboptimal assignment of pins to grounds and signals, the ground noise problem in integrated circuit (ICs) packages either persists or compromises the design by forcing too many pins to be wasted carrying ground reference. This paper proposes a new CAD technique for optimizing pin assignment in IC packages to minimize ground noise using simulated annealing. Optimization techniques are used in which the objective function is the ground noise as determined by simulation of the IC package leadframe. However, modeling and simulation methods currently employed are prohibitively expensive in terms of CPU time. For this reason, two circuit models of the leadframe are developed and used concurrently: one to provide accuracy and the other to ensure fast execution. Using simulated annealing with a ground noise cost function has provided an observed 26-fold reduction in ground noise in a 208-pin IC quad flat pack (QFP) from a poor initial configuration. In addition, the same process was able to produce a 2.2-fold improvement when an intelligent initial pin assignment was used. Furthermore, these results came at a CPU cost of about 1200 s each on a SUN SPARC10 workstation.

[1]  Q.J. Zhang,et al.  Ground noise estimation and minimization in integrated circuit packages , 1993, 1993 International Symposium on Electromagnetic Compatibility.

[2]  C. D. Gelatt,et al.  Optimization by Simulated Annealing , 1983, Science.

[3]  C. Durney,et al.  Extending the two-dimensional FDTD method to hybrid electromagnetic systems with active and passive lumped elements , 1992 .

[4]  Peter P. Silvester,et al.  Finite Elements for Electrical Engineers , 1983 .

[5]  John L. Prince,et al.  Simultaneous Switching Noise of CMOS Devices and Systems , 1993 .

[6]  Albert E. Ruehli,et al.  The modified nodal approach to network analysis , 1975 .

[7]  Roger F. Harrington,et al.  Field computation by moment methods , 1968 .

[8]  Andreas C. Cangellaris,et al.  Modeling and simulation of coupled transmission line interconnects over a noisy reference plane , 1993 .

[9]  C. R. Paul,et al.  Effect of an image plane on printed circuit board radiation , 1990, IEEE International Symposium on Electromagnetic Compatibility.

[10]  A. J. Rainal Computing inductive noise of chip packages , 1984, AT&T Bell Laboratories Technical Journal.

[11]  M. Chari,et al.  Finite elements in electrical and magnetic field problems , 1980 .

[12]  O. Zienkiewicz The Finite Element Method In Engineering Science , 1971 .

[13]  Rob A. Rutenbar,et al.  Simulated annealing algorithms: an overview , 1989, IEEE Circuits and Devices Magazine.

[14]  Mattan Kamon,et al.  FASTHENRY: a multipole-accelerated 3-D inductance extraction program , 1994 .

[15]  Raj Mittra,et al.  A general purpose Maxwell solver for the extraction of equivalent circuits of electronic package components for circuit simulation , 1992 .

[16]  Albert E. Ruehli,et al.  Inductance calculations in a complex integrated circuit environment , 1972 .

[17]  I. J. Sorkin,et al.  A Method of Using Audio Signal-to-Noise Measurements to Obtain Criterion Contours for the Probability Scoring Model for Scoring Voice Communications Reception , 1968 .