A complete dynamic power estimation model for data-paths in FPGA DSP designs

A complete model for estimating power consumption in DSP-oriented designs implemented in FPGAs is presented. The model consists of three submodels. One is used for power estimation of the global routing employed for interconnections between the components. It depends on their mutual distance and shape. The other estimates clock power and depends on the estimated design area. The remaining model is used for both local interconnect and logic power estimation of the components. It is based on the analytical computation of the switching activity produced inside the component in the presence of correlated inputs. The complete model has been characterized and verified by on-board power measurements, instead of using low-level estimation tools which often lack the required accuracy. The results show that the mean relative error of each individual submodel always lies within 10% of the physical measurements, while the complete model has a mean relative error of only 12%.

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