Realization of over 650V double RESURF LDMOS with HVI for high side gate drive IC

The two structures of over 650V MR & MR SLMFFP double RESURF LDMOSs with HVI are experimentally realized using SPSM BCD process for high side gate drive IC. The experimental results, coincident with the three-dimensional simulations, show that the breakdown voltage of LDMOS will increase by reducing the width of HVI metal line. The breakdown voltages of the MR double RESURF LDMOS are 670V, 760V, 990V when the widths of HVI metal lines are 20 mum, 5 mum, 0 mum, respectively. The breakdown voltages of the MR SLMFFP double RESURF LDMOS are 700V, 920V when the widths of HVI metal lines are 15 mum, 0 mum, respectively. An experimental half bridge gate drive IC is also successfully implemented, using the MR double RESURF LDMOS with HVI. As a result, the two proposed high voltage structures can be used in level shifting and HVJT for AC260V, without thick oxide and additional conductive layer

[1]  W. Gerlach,et al.  Influence of interconnections onto the breakdown voltage of planar high-voltage p-n junctions , 1993 .

[2]  J. Moritani,et al.  A 600V HVIC process with a built-in EPROM which enables new concept gate driving , 2004, 2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs.

[3]  A.F.J. Murray,et al.  Optimization of interconnection-induced breakdown voltage in junction isolated IC's using biased polysilicon field plates , 1997 .

[4]  T. Yamada,et al.  Over 1000 V n-ch LDMOSFET and p-ch LIGBT with JI RESURF structure and multiple floating field plate , 1995, Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95.

[5]  K. Endo,et al.  A 500 V 1A 1-chip inverter IC with a new electric field reduction structure , 1994, Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics.