Run-Time Task Allocation Considering User Behavior in Embedded Multiprocessor Networks-on-Chip

In this paper, we propose a run-time strategy for allocating application tasks to embedded multiprocessor systems-on-chip platforms where communication happens via the network-on-chip approach. As a novel contribution, we incorporate the user behavior information in the resource allocation process; this allows the system to better respond to real-time changes and to adapt dynamically to different user needs. Several algorithms are proposed for solving the task allocation problem while minimizing the communication energy consumption and network contention. When the user behavior is taken into consideration, we observe more than 70% communication energy savings (with negligible energy and run-time overhead) compared to an arbitrary contiguous task allocation strategy.

[1]  Cynthia A. Phillips,et al.  Communication-Aware Processor Allocation for Supercomputers , 2005, WADS.

[2]  Rabi N. Mahapatra,et al.  A heuristic for peak power constrained design of network-on-chip (NoC) based multimode systems , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

[3]  Ron Kohavi,et al.  A Study of Cross-Validation and Bootstrap for Accuracy Estimation and Model Selection , 1995, IJCAI.

[4]  Radu Marculescu,et al.  User-Aware Dynamic Task Allocation in Networks-on-Chip , 2008, 2008 Design, Automation and Test in Europe.

[5]  Jens Mache,et al.  Dispersal Metrics for Non-Contiguous Processor Allocation , 1996 .

[6]  Bill Nitzberg,et al.  Non-contiguous processor allocation algorithms for distributed memory multicomputers , 1994, Proceedings of Supercomputing '94.

[7]  Henry Hoffmann,et al.  On-Chip Interconnection Architecture of the Tile Processor , 2007, IEEE Micro.

[8]  Natalie D. Enright Jerger,et al.  Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Sander Stuijk,et al.  Parallel implementation of arbitrary-shaped MPEG-4 decoder for multiprocessor systems , 2006, Electronic Imaging.

[10]  Orlando Moreira,et al.  Online resource management in a multiprocessor with a network-on-chip , 2007, SAC '07.

[11]  Diederik Verkest,et al.  Operating-system controlled network on chip , 2004, Proceedings. 41st Design Automation Conference, 2004..

[12]  Anant Agarwal,et al.  The KILL Rule for Multicore , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[13]  Petru Eles,et al.  An approach to incremental design of distributed embedded systems , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[14]  Luca Benini,et al.  Networks on chip: a new paradigm for systems on chip design , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[15]  V. Lo,et al.  Contiguous and Non-contiguous Processor Allocation , 1995 .

[16]  Radu Marculescu,et al.  Energy- and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[17]  Bill N. Schilit,et al.  Context-aware computing applications , 1994, Workshop on Mobile Computing Systems and Applications.

[18]  William J. Dally,et al.  Deadlock-Free Message Routing in Multiprocessor Interconnection Networks , 1987, IEEE Transactions on Computers.

[19]  Srinivasan Murali,et al.  Bandwidth-constrained mapping of cores onto NoC architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[20]  Daniël Paulusma,et al.  Run-time assignment of tasks to multiple heterogeneous processors , 2004 .

[21]  B. Efron Estimating the Error Rate of a Prediction Rule: Improvement on Cross-Validation , 1983 .

[22]  Keqin Li,et al.  A Two-Dimensional Buddy System for Dynamic Resource Allocation in a Partitionable Mesh Connected System , 1991, J. Parallel Distributed Comput..

[23]  Théodore Marescaux,et al.  Centralized run-time resource management in a network-on-chip containing reconfigurable hardware tiles , 2005, Design, Automation and Test in Europe.

[24]  L. Benini,et al.  Analysis of power consumption on switch fabrics in network routers , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[25]  Coniferous softwood GENERAL TERMS , 2003 .

[26]  Bella Bose,et al.  Contiguous and Non-Contiguous Processor Allocation Algorithms for kappa-cubes , 1995, ICPP.

[27]  Srinivasan Murali,et al.  A Methodology for Mapping Multiple Use-Cases onto Networks on Chips , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[28]  Sriram R. Vangal,et al.  A 5-GHz Mesh Interconnect for a Teraflops Processor , 2007, IEEE Micro.

[29]  Radu Marculescu,et al.  Application-specific buffer space allocation for networks-on-chip router design , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[30]  E. Demaine,et al.  What is the optimal shape of a city , 2004 .

[31]  J. Kao DETC 98 / CIE-5699 OPTIMAL MOTION PLANNING FOR DEPOSITION IN LAYERED MANUFACTURING , 1998 .