Software-Based Test for Non-Programmable Cores in Bus-Based System-on-Chip Architectures

With the advance in hardware integration, system-on-a-chip (SoC) test activities using only automatic test equipments (ATEs) result in an expensive option. Hardware-based test may reduce the ATE dependency. However, hardware-based test imposes some constraints like area overhead and processing speed degradation. The main objective of this work is to investigate and evaluate a less intrusive test approach called software-based test. Software-based test uses an embedded processor as source and sink of the test, sending the test patterns and reading the responses. A new integrated design and test environment has been developed to automatically synthesize test programs to test non-programmable cores of SoCs. Some benchmarks ISCAS85 and ISCAS89 are used to evaluate the proposed methodology.

[1]  Ad J. van de Goor,et al.  Using March Tests to Test SRAMs , 1993, IEEE Des. Test Comput..

[2]  Sujit Dey,et al.  Software-based self-testing methodology for processor cores , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Janusz Rajski,et al.  Arithmetic Built-In Self-Test for Embedded Systems , 1997 .

[4]  Yervant Zorian,et al.  Low-Cost Software-Based Self-Testing of RISC Processor Cores , 2003, DATE.

[5]  Kwang-Ting Cheng,et al.  Instruction-level DFT for testing processor and IP cores in system-on-a-chip , 2001, DAC '01.

[6]  Nur A. Touba,et al.  Reducing test data volume using LFSR reseeding with seed compression , 2002, Proceedings. International Test Conference.

[7]  Jacob A. Abraham,et al.  A METHODOLOGY FOR FUNCTIONAL LEVEL TESTING OF MICROPROCESSORS , 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing, 1995, ' Highlights from Twenty-Five Years'..

[8]  Kwang-Ting Cheng,et al.  A self-test methodology for IP cores in bus-based programmable SoCs , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[9]  Yervant Zorian,et al.  An Effective BIST Scheme for ROM's , 1992, IEEE Trans. Computers.

[10]  Alexandre M. Amory,et al.  Reducing test time with processor reuse in network-on-chip based systems , 2004, Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784).

[11]  Jacob A. Abraham,et al.  Reuse of addressable system bus for SOC testing , 2001, Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558).

[12]  Hans-Joachim Wunderlich,et al.  Mixed-Mode BIST Using Embedded Processors , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[13]  Sujit Dey,et al.  Embedded Software-Based Self-Test for Programmable Core-Based Designs , 2002, IEEE Des. Test Comput..