Impact of Self-Heating on the Statistical Variability in Bulk and SOI FinFETs

In this paper, for the first time, we study the impact of self-heating on the statistical variability of bulk and Silicon-on-insulator FinFETs designed to meet the requirements of the 14/16-nm technology node. The simulations are performed using the Gold Standard Simulations atomistic simulator GARAND using an enhanced electrothermal model that considers the impact of the fin geometry on the thermal conductivity. In the simulations, we have compared the statistical variability obtained from full-scale electrothermal simulations with the variability at uniform room temperature and at the maximum or average temperatures obtained in the electrothermal simulations. The combined effects of line edge roughness and metal gate granularity are considered. The distributions and the correlations between key figures of merit, including the threshold voltage, ON-current, subthreshold slope, and leakage current are presented and analyzed.

[1]  R. E. Thomas,et al.  Carrier mobilities in silicon empirically related to doping and field , 1967 .

[2]  G. Masetti,et al.  Modeling of carrier mobility against carrier concentration in arsenic-, phosphorus-, and boron-doped silicon , 1983, IEEE Transactions on Electron Devices.

[3]  Massimo Vanzi,et al.  A physically based mobility model for numerical simulation of nonplanar devices , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  A. Asenov,et al.  Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness , 2003 .

[5]  Ching-Te Chuang,et al.  Self-Consistent and Efficient Electro-Thermal Analysis for Poly/Metal Gate FinFETs , 2006, 2006 International Electron Devices Meeting.

[6]  K. Endo,et al.  Modeling and Analysis of Self-Heating in FinFET Devices for Improved Circuit and EOS/ESD Performance , 2007, 2007 IEEE International Electron Devices Meeting.

[7]  Y. Nara,et al.  Impact of additional factors in threshold voltage variability of metal/high-k gate stacks and its reduction by controlling crystalline structure and grain size in the metal gates , 2008, 2008 IEEE International Electron Devices Meeting.

[8]  K. Banerjee,et al.  Modeling and analysis of grain-orientation effects in emerging metal-gate devices and implications for SRAM reliability , 2008, 2008 IEEE International Electron Devices Meeting.

[9]  C. Fiegna,et al.  Simulation of self-heating effects in 30nm gate length FinFET , 2008, 2008 9th International Conference on Ultimate Integration of Silicon.

[10]  G.D.J. Smit,et al.  Experimental assessment of self-heating in SOI FinFETs , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[11]  Andrew R. Brown,et al.  Impact of Metal Gate Granularity on Threshold Voltage Variability: A Full-Scale Three-Dimensional Statistical Simulation Study , 2010, IEEE Electron Device Letters.

[12]  D. Vasileska,et al.  Electrothermal Studies of FD SOI Devices That Utilize a New Theoretical Model for the Temperature and Thickness Dependence of the Thermal Conductivity , 2010, IEEE Transactions on Electron Devices.

[13]  M. Belleville,et al.  On the Variability in Planar FDSOI Technology: From MOSFETs to SRAM Cells , 2011, IEEE Transactions on Electron Devices.

[14]  M. Belleville,et al.  Drain current variability and MOSFET parameters correlations in planar FDSOI technology , 2011, 2011 International Electron Devices Meeting.

[15]  A. Asenov,et al.  Statistical Threshold-Voltage Variability in Scaled Decananometer Bulk HKMG MOSFETs: A Full-Scale 3-D Simulation Scaling Study , 2011, IEEE Transactions on Electron Devices.

[16]  Andrew R. Brown,et al.  Statistical variability in 14-nm node SOI FinFETs and its impact on corresponding 6T-SRAM cell design , 2012, 2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

[17]  M. Shrivastava,et al.  Physical Insight Toward Heat Transport and an Improved Electrothermal Modeling Framework for FinFET Architectures , 2012, IEEE Transactions on Electron Devices.

[18]  Chris Auth,et al.  22-nm fully-depleted tri-gate CMOS transistors , 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.

[19]  A. Asenov,et al.  Statistical variability study of a 10nm gate length SOI FinFET device , 2012, 2012 IEEE Silicon Nanoelectronics Workshop (SNW).

[20]  Kaustav Banerjee,et al.  Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[21]  Asen Asenov,et al.  Comparative Simulation Analysis of Process-Induced Variability in Nanoscale SOI and Bulk Trigate FinFETs , 2013, IEEE Transactions on Electron Devices.

[22]  3D coupled electro-thermal simulations for SOI FinFET with statistical variations including the fin shape dependence of the thermal conductivity , 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).