Selective Pseudo Scan - Combinational Atpg with Reduced Scan in a Full Custom Risc Microprocessor

This paper presents a novel test generation technique, called Selective Pseudo Scan (SPS), which incurs very low overhead. SPS uses a commercial combinational ATPG tool to generate tests with high fault coverage by reconfiguring sequential circuits to appear combinational without inserting scan. Results of applying SPS to several complex control blocks of a full custom RISC Microprocessor, demonstrate its superiority compared to traditional full scan or partial scan in a full custom design environment.

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