A SYNTHESIS AND OPTIMIZATION PROCEDURE FOR FULLY TESTABLE SEQUENTIAL MACHINES

In this paper, we outline a synthesis procedure which beginning from a State Transition Graph description of a sequential machine produces an optimized fully testable logic implementa tion. This logic-level implementation is guaranteed to be testable for all single stuck-at faults and the test sequences for these faults can be obtained using combinational test generation techniques alone. All single stuck-at faults in the synthesized logic-level automaton can be tested without access to the memory elements using these test sequences. Thus, the testing time required is smaller than that using a Scan Design methodology. The area penalty incurred due to the con straints on the optimization are small. The performance of the synthesized design is usually better man a unconstrained design optimized for area alone. The relationship between combinational logic optimization and combinational test generation is well known. In this paper, we show mat an intimate relationship exists between state assignment and the testability of a sequential machine. We propose a procedure of constrained state assign ment and logic optimization which guarantees testability for both Moore and Mealy machines. We present results which illustrate the efficacy of this procedure the area/performance penalties in return for 100% testability are negligible. Acknowledgements This work is supported in part by the Semiconductor Research Corporation, the Defense Advanced Research Projects Agency under contract N00039-86-R-0365 and a grant from AT&T Bell Laboratories. Their support is gratefully acknowledged.