Low-power 3D nano/CMOS hybrid dynamically reconfigurable architecture
暂无分享,去创建一个
[1] Wei Zhang,et al. ALLCN: an automatic logic-to-layout tool for carbon nanotube based nanotechnology , 2005, 2005 International Conference on Computer Design.
[2] H. Hamann,et al. Ultra-high-density phase-change storage and memory , 2006, Nature materials.
[3] Seth Copen Goldstein,et al. PipeRench: A Reconfigurable Architecture and Compiler , 2000, Computer.
[4] Jonathan Rose,et al. Measuring the Gap Between FPGAs and ASICs , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[5] Wei Zhang,et al. A hybrid nano/CMOS dynamically reconfigurable system—Part I: Architecture , 2009, JETC.
[6] Jian Xu,et al. Demystifying 3D ICs: the pros and cons of going vertical , 2005, IEEE Design & Test of Computers.
[7] Wei Wang,et al. Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture , 2007, ICCAD 2007.
[8] Jonathan Rose,et al. Measuring the Gap Between FPGAs and ASICs , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[9] M. Motomura,et al. Reconfigurable computing: its concept and a practical embodiment using newly developed dynamically reconfigurable logic (DRL) LSI , 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).
[10] Wei Zhang,et al. NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture , 2007, 2007 44th ACM/IEEE Design Automation Conference.
[11] Charles M. Lieber,et al. Carbon nanotube-based nonvolatile random access memory for molecular computing , 2000, Science.
[12] Anish Muttreja,et al. CMOS logic design with independent-gate FinFETs , 2007, 2007 25th International Conference on Computer Design.
[13] Vaughn Betz,et al. VPR: A new packing, placement and routing tool for FPGA research , 1997, FPL.
[14] D. Strukov,et al. CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices , 2005 .
[15] Li Shang,et al. Towards An Ultra-Low-Power Architecture Using Single-Electron Tunneling Transistors , 2007, 2007 44th ACM/IEEE Design Automation Conference.
[16] Nathaniel S. Borenstein,et al. IBM ® , 2009 .
[17] Paul Beckett,et al. A Low-Power Reconfigurable Logic Array Based on Double-Gate Transistors , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[18] André DeHon,et al. Dynamically Programmable Gate Arrays: A Step Toward Increased Computational Density , 1996 .
[19] Roy Yu. High density 3D integration , 2008, 2008 International Conference on Electronic Packaging Technology & High Density Packaging.
[20] R. Williams,et al. Nano/CMOS architectures using a field-programmable nanowire interconnect , 2007 .
[21] Wei Zhang,et al. Design space exploration and data memory architecture design for a hybrid nano/CMOS dynamically reconfigurable architecture , 2009, JETC.
[22] Charles M. Lieber,et al. High Performance Silicon Nanowire Field Effect Transistors , 2003 .
[23] Wei Wang,et al. Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.
[24] M. Koyanagi,et al. Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections , 2006, IEEE Transactions on Electron Devices.
[25] S. Lai,et al. Current status of the phase change memory and its future , 2003, IEEE International Electron Devices Meeting 2003.
[26] Wei Zhang,et al. A hybrid Nano/CMOS dynamically reconfigurable system—Part II: Design optimization flow , 2009, JETC.
[27] ZhangWei,et al. Low-power 3D nano/CMOS hybrid dynamically reconfigurable architecture , 2010 .
[28] Jing Guo,et al. Carbon Nanotube Field-Effect Transistors with Integrated Ohmic Contacts and High-κ Gate Dielectrics , 2004 .
[29] Wei Zhang,et al. NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[30] Srivaths Ravi,et al. Satisfiability-based test generation for nonseparable RTL controller-datapath circuits , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[31] Kaushik Roy,et al. Double-gate SOI devices for low-power and high-performance applications , 2005, ICCAD.
[32] Michael J. Wilson,et al. Nanowire-based sublithographic programmable logic arrays , 2004, FPGA '04.
[33] Katsuyuki Sakuma,et al. Three-dimensional silicon integration , 2008, IBM J. Res. Dev..
[34] Konstantin K. Likharev,et al. Single-electron devices and their applications , 1999, Proc. IEEE.
[35] R. Stanley Williams,et al. CMOS-like logic in defective, nanoscale crossbars , 2004 .
[36] Mohab Anis,et al. Dual-Vt design of FPGAs for subthreshold leakage tolerance , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).
[37] Pierre G. Paulin,et al. Force-directed scheduling for the behavioral synthesis of ASICs , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[38] Steven M. Nowick,et al. ACM Journal on Emerging Technologies in Computing Systems , 2010, TODE.
[39] Srivaths Ravi,et al. Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications , 2003, ICCAD 2003.
[40] Hyungsoon Shin,et al. Macro model and sense amplifier for a MRAM , 2002 .
[41] Hyungsoon Shin,et al. Advanced HSPICE Macromodel for Magnetic Tunnel Junction , 2005 .
[42] Weidong Xu,et al. Rothko: A Three-Dimensional FPGA , 1998, IEEE Des. Test Comput..
[43] Niraj K. Jha,et al. Hierarchical test generation and design for testability methods for ASPPs and ASIPs , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[44] Hanpei Koike,et al. Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGA , 2007, IEICE Trans. Inf. Syst..
[45] Yiran Chen,et al. Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement , 2008, 2008 45th ACM/IEEE Design Automation Conference.
[46] Mingjie Lin,et al. Performance Benefits of Monolithically Stacked 3-D FPGA , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[47] Mei Liu,et al. Three-dimensional CMOL: three-dimensional integration of CMOS/nanomaterial hybrid digital circuits , 2007 .
[48] Steven Trimberger,et al. A time-multiplexed FPGA , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).
[49] Mark Mohammad Tehranipoor,et al. A new hybrid FPGA with nanoscale clusters and CMOS routing , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[50] M. Hosomi,et al. A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
[51] E. Belhaire,et al. Macro-model of Spin-Transfer Torque based Magnetic Tunnel Junction device for hybrid Magnetic-CMOS design , 2006, 2006 IEEE International Behavioral Modeling and Simulation Workshop.
[52] A. Kumar,et al. Back-gated SOI technology: power-adaptive logic and non-volatile memory using identical processing , 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).
[53] E.J. Nowak,et al. Turning silicon on its edge [double gate CMOS/FinFET technology] , 2004, IEEE Circuits and Devices Magazine.
[54] Jon M. Slaughter,et al. Magnetoresistive random access memory using magnetic tunnel junctions , 2003, Proc. IEEE.
[55] Fei Li,et al. FPGA power reduction using configurable dual-Vdd , 2004, Proceedings. 41st Design Automation Conference, 2004..
[56] S. Perissakis,et al. Embedded DRAM for a reconfigurable array , 1999, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).
[57] A. Pirovano,et al. A Phase Change Memory Compact Model for Multilevel Applications , 2007, IEEE Electron Device Letters.
[58] Edmund J. Sprogis,et al. Wafer-level 3D integration technology , 2008, IBM J. Res. Dev..
[59] Raphael Rubin,et al. 3D Nanowire-Based Programmable Logic , 2006, 2006 1st International Conference on Nano-Networks and Workshops.