Effect of technology scaling on RF performance of the transistors fabricated by standard CMOS technology
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Chulho Chung | HyunWoo Lee | Han-Su Kim | Jong Shik Yoon | Hansu Oh | Gwangdoo Jo | Jedon Kim | Joohyun Jeong | Seung-Jae Jung | Jinsung Lim | JinHyoun Joe | Jaehoon Park | Kangwook Park
[1] Chih-Sheng Chang,et al. Pocket implantation effect on drain current flicker noise in analog nMOSFET devices , 2004, IEEE Transactions on Electron Devices.
[2] F. Danneville,et al. What are the limiting parameters of deep-submicron MOSFETs for high frequency applications? , 2003, IEEE Electron Device Letters.
[3] K. Narasimhulu,et al. Impact of lateral asymmetric channel doping on deep submicrometer mixed-signal device and circuit performance , 2003 .
[4] B. Jagannathan,et al. Record RF performance of sub-46 nm L/sub gate/ NFETs in microprocessor SOI CMOS technologies , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
[5] M. Breitwisch,et al. High-performance logic and high-gain analog CMOS transistors formed by a shadow-mask technique with a single implant step , 2002 .