A system level boundary scan controller board for VME applications [to CERN experiments]

This work is the result of a collaboration between INESC and LIP in the CMS experiment being conducted at CERN. The collaboration addresses the application of boundary scan test at system level namely the development of a VME boundary scan controller (BSC) board prototype and the corresponding software. This prototype uses the MTM bus existing in the VME64/spl times/ backplane to apply the 1149.1 test vectors to a system composed of nineteen boards, called here units under test (UUTs). A top-down approach is used to describe our work. The paper begins with some insights about the experiment being conducted at CERN, proceed with system level considerations concerning our work and with some details about the BSC board. The results obtained so far and the proposed work is reviewed in the end of this contribution.

[1]  David L. Landis,et al.  Applications of the IEEE P1149.5 module test and maintenance bus , 1992, Proceedings International Test Conference 1992.

[2]  Marcelino B. Santos,et al.  TESTABILITY ISSUES IN THE CMS ECAL UPPER-LEVEL READOUT AND TRIGGER SYSTEM , 2000 .

[3]  Wuudiann Ke.  Backplane interconnect test in a boundary-scan environment , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[4]  C. Champlin.  IRIDIUM satellite: A large system application of design for testability , 1993, Proceedings of IEEE International Test Conference - (ITC).