Diagnosis of Interconnect Full Open Defects in the Presence of Fan-Out

The development of accurate diagnosis methodologies is important to identify process problems and achieve fast yield improvement. As open defects are becoming dominant in some CMOS technologies, their accurate diagnosis is key to improving the quality of new very large-scale integrated circuits. Widely used interconnect full open diagnosis procedures are based on the assumption that neighboring lines determine the voltage of the defective line. However, this assumption decreases the diagnosis efficiency for opens in interconnect lines with fan-out, where the influence of transistor capacitances is significant. This paper presents a diagnosis methodology for interconnect full open defects which considers and models the impact of transistor parasitic capacitances on the defective node accurately. The methodology is able to properly diagnose interconnect opens with fan-out even in the presence of Byzantine behavior. Diagnosis results for real defective devices from different technology nodes are also provided.

[1]  Srikanth Venkataraman,et al.  Poirot: Applications of a Logic Fault Diagnosis Tool , 2001, IEEE Des. Test Comput..

[2]  Kenneth M. Thompson.  Intel and the Myths of Test , 1996, IEEE Des. Test Comput..

[3]  Masaki Hashizume,et al.  A Novel Approach for Improving the Quality of Open Fault Diagnosis , 2009, 2009 22nd International Conference on VLSI Design.

[4]  Camelia Hora,et al.  Full Open Defects in Nanometric CMOS , 2008, 26th IEEE VLSI Test Symposium (vts 2008).

[5]  C. Hora,et al.  Impact of gate tunnelling leakage on CMOS circuits with full open defects , 2007 .

[6]  Camelia Hora,et al.  Diagnosis of full open defects in interconnect lines with fan-out , 2010, 2010 15th IEEE European Test Symposium.

[7]  Haluk Konuk.  Voltage- and current-based fault simulation for interconnect open defects , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  S.M. Reddy,et al.  Interconnect Open Defect Diagnosis with Physical Information , 2006, 2006 15th Asian Test Symposium.

[9]  Daniel Arumí,et al.  Experimental Characterization of CMOS Interconnect Open Defects , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Sudhakar M. Reddy,et al.  Interconnect open defect diagnosis with minimal physical information , 2007, 2007 IEEE International Test Conference.

[11]  Masahiro Takakura,et al.  A persistent diagnostic technique for unstable defects , 2002, Proceedings. International Test Conference.

[12]  Shi-Yu Huang.  Diagnosis of Byzantine open-segment faults [scan testing] , 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

[13]  Tracy Larrabee,et al.  Beyond the byzantine generals: unexpected behavior and bridging fault diagnosis , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[14]  Hiroshi Takahashi,et al.  Incremental diagnosis of multiple open-interconnects , 2002, Proceedings. International Test Conference.

[15]  Masaki Hashizume,et al.  Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC , 2009, 2009 22nd International Conference on VLSI Design.

[16]  M. Lousberg,et al.  On Electrical Fault Diagnosis in Full-Scan Circuits , 2001 .

[17]  Antonio Rubio,et al.  Electrical model of the floating gate defect in CMOS ICs: implications on IDDQ testing , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  Víctor H. Champac,et al.  Detectability conditions for interconnection open defects , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[19]  A. Stamper,et al.  Sub-0.25-micron interconnection scaling: damascene copper versus subtractive aluminum , 1998, IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168).

[20]  M. Renovell,et al.  Topology dependence of floating gate faults in MOS integrated circuits , 1986 .

[21]  Simon Johnson,et al.  Residual charge on the faulty floating gate CMOS transistor , 1994, Proceedings., International Test Conference.

[22]  Michel Renovell,et al.  A new methodology for realistic open defect detection probability evaluation under process variations , 2011, 29th VLSI Test Symposium.

[23]  Y. Sato,et al.  Defect Diagnosis - Reasoning Methodology , 2006, 2006 15th Asian Test Symposium.

[24]  Charles F. Hawkins,et al.  THE BEHAVIOR AND TESTING IMPLICATIONS OF CMOS IC LOGIC GATE OPEN CIRCUITS , 1991, 1991, Proceedings. International Test Conference.

[25]  Camelia Hora,et al.  Time-dependent Behaviour of Full Open Defects in Interconnect Lines , 2008, 2008 IEEE International Test Conference.

[26]  Michele Favalli,et al.  Modeling and simulation of broken connections in CMOS IC's , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[27]  Jochen A. G. Jess,et al.  Probability analysis for CMOS floating gate faults , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[28]  F. Joel Ferguson,et al.  An unexpected factor in testing for CMOS opens: the die surface , 1996, Proceedings of 14th VLSI Test Symposium.

[29]  Bernd Becker,et al.  Diagnosis of Realistic Defects Based on the X-Fault Model , 2008, 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems.

[30]  André Ivanov,et al.  Testing for floating gates defects in CMOS circuits , 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

[31]  Irith Pomeranz,et al.  On tests to detect via opens in digital CMOS circuits , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[32]  Camelia Hora,et al.  Diagnosis of Full Open Defects in Interconnecting Lines , 2007, 25th IEEE VLSI Test Symposium (VTS'07).

[33]  Ieee Circuits,et al.  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[34]  Rosa Rodríguez-Montañés,et al.  Resistance characterization for weak open defects , 2002, IEEE Design & Test of Computers.