Designs of PMC-based non-volatile memory circuits for data restoring

This paper presents two circuits for implementing the restore operation of a non-volatile (NV) memory cell in which data from a programmable metallization cell (PMC) can be copied (restored) into a static random access memory (SRAM). In the first proposed design, a transmission gate is added to each row of cells of the memory array in which a concurrent error detection (CED) circuit is also present. When a mismatch between the data stored in the SRAM and the PMC is detected, the restore operation starts for a single cell. For the second proposed design, a tri-state inverter is added to control the restore operation. This design requires a larger circuit complexity compared to the first design, but performance is substantially improved; moreover, all cells of a memory array can be simultaneously restored, thus suitable for restarting with power-on. A comparison of these designs with a previous scheme is also pursued; it is shown that the proposed designs improve performance.

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