Novel Superjunction LDMOS (>950 V) With a Thin Layer SOI

A novel superjunction (SJ) lateral double-diffused MOSFET (>950 V) with a thin layer SOI combining the advantage of low specific on-resistance <inline-formula> <tex-math notation="LaTeX">${R}_{\text {on,sp}}$ </tex-math></inline-formula> of the SJ and the high breakdown voltage <inline-formula> <tex-math notation="LaTeX">${V}_{\text {B}}$ </tex-math></inline-formula> of the thin SOI is proposed and experimentally demonstrated in this letter. Based on our previously developed equivalent substrate model, the optimized SJ endows the device with a respectably reduced <inline-formula> <tex-math notation="LaTeX">${R}_{\text {on,sp}}$ </tex-math></inline-formula> without sacrificing <inline-formula> <tex-math notation="LaTeX">${V}_{\text {B}}$ </tex-math></inline-formula>. Meanwhile, the thin layer SOI is designed with the enhanced dielectric layer field principle to carry out a high <inline-formula> <tex-math notation="LaTeX">${V}_{\text {B}}$ </tex-math></inline-formula>. The experimental results exhibit a <inline-formula> <tex-math notation="LaTeX">${R}_{\text {on,sp}}$ </tex-math></inline-formula> of 145 <inline-formula> <tex-math notation="LaTeX">$\text{m}\Omega \cdot $ </tex-math></inline-formula>cm<sup>2</sup> with a <inline-formula> <tex-math notation="LaTeX">${V}_{\text {B}}$ </tex-math></inline-formula> of 977 V. This represents a reduction in <inline-formula> <tex-math notation="LaTeX">${R}_{\text {on,sp}}$ </tex-math></inline-formula> by 18.1% when compared with the theoretical <inline-formula> <tex-math notation="LaTeX">${R}_{\text {on,sp}} \propto {V}_{\text {B}}^{{2.5}}\vphantom {^{^{^{^{}}}}}$ </tex-math></inline-formula> “silicon limit”.

[1]  T. Oda,et al.  Low on-resistance high voltage thin layer SOI LDMOS transistors with stepped field plates , 2017, 2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD).

[2]  Xinhong Cheng,et al.  Realization of 850V breakdown voltage LDMOS on Simbond SOI , 2012 .

[3]  B. J. Baliga,et al.  Analysis of silicon carbide power device performance , 1991, [1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs.

[4]  F. Udrea,et al.  Compact three-dimensional silicon termination solutions for high voltage SOI SuperJunction , 2012, 2012 24th International Symposium on Power Semiconductor Devices and ICs.

[5]  C.A.T. Salama,et al.  150-V class superjunction power LDMOS transistor switch on SOI , 2002, Proceedings of the 14th International Symposium on Power Semiconductor Devices and Ics.

[7]  B. Zhang,et al.  Theory of Superjunction With NFD and FD Modes Based on Normalized Breakdown Voltage , 2015, IEEE Transactions on Electron Devices.

[8]  T. Letavic,et al.  High performance 600 V smart power technology based on thin layer silicon-on-insulator , 1997, Proceedings of 9th International Symposium on Power Semiconductor Devices and IC's.

[9]  吴丽娟,et al.  Breakdown voltage model and structure realization of a thin silicon layer with linear variable doping on a silicon on insulator high voltage device with multiple step field plates , 2012 .

[10]  Bo Zhang,et al.  Field Enhancement for Dielectric Layer of High-Voltage Devices on Silicon on Insulator , 2009, IEEE Transactions on Electron Devices.

[11]  B. Zhang,et al.  A Novel Vertical Field Plate Lateral Device With Ultralow Specific On-Resistance , 2014, IEEE Transactions on Electron Devices.

[12]  Shengdong Zhang,et al.  Numerical modeling of linear doping profiles for high-voltage thin-film SOI devices , 1999 .

[13]  Bo Zhang,et al.  Equivalent Substrate Model for Lateral Super Junction Device , 2014, IEEE Transactions on Electron Devices.

[14]  P. Hui,et al.  A high voltage Super-Junction NLDMOS device implemented in 0.13µm SOI based Smart Power IC technology , 2010, 2010 22nd International Symposium on Power Semiconductor Devices & IC's (ISPSD).

[15]  B. Zhang,et al.  Optimization of Lateral Superjunction Based on the Minimum Specific ON-Resistance , 2016, IEEE Transactions on Electron Devices.

[16]  B. Zhang,et al.  The $R_{\mathrm{\scriptscriptstyle ON},\mathrm {min}}$ of Balanced Symmetric Vertical Super Junction Based on R-Well Model , 2017, IEEE Transactions on Electron Devices.

[17]  D. Takacs,et al.  A dielectric isolated high-voltage IC-technology for off-line applications , 1995, Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95.