Design, Implementation, and Test of a Multi-Model Systolic Neural-Network Accelerator

Keywords: neurone ; Non-Linear Modelling ; Neural Network Reference LANOS-CONF-1994-018 Record created on 2004-12-03, modified on 2016-08-08

[1]  Dagmar Niebur,et al.  Unsupervised Neural Net Classification of Power System Static Security States , 1991 .

[2]  Patrick Thiran,et al.  Self-organization of a one-dimensional Kohonen network with quantized weights and inputs , 1994, Neural Networks.

[3]  Paolo Ienne,et al.  A Systolic Accelerator for Power System Security Assessment , 1994 .

[4]  P. Ienne,et al.  Performance of digital neuro-computers , 1994, Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems.

[5]  Marc Viredaz.  Design and analysis of a systolic array for neural computation , 1994 .

[6]  Paolo Ienne,et al.  GENES IV: A bit-serial processing element for a multi-model neural-network accelerator , 1993, J. VLSI Signal Process..

[7]  Patrick Thiran,et al.  Quantization effects in digitally behaving circuit implementations of Kohonen networks , 1994, IEEE Trans. Neural Networks.

[8]  Teuvo Kohonen,et al.  Self-organization and associative memory: 3rd edition , 1989 .

[9]  Paolo Ienne,et al.  Digital systems for neural networks , 1995, Defense + Commercial Sensing.

[10]  Paolo Ienne,et al.  Modified self-organizing feature map algorithms for efficient digital hardware implementation , 1997, IEEE Trans. Neural Networks.

[11]  Ulrich Ramacher,et al.  SYNAPSE - A Neurocomputer that Synthesizes Neural Algorithms on a Parallel Systolic Engine , 1992, J. Parallel Distributed Comput..

[12]  Paolo Ienne,et al.  Horizontal microcode compaction for programmable systolic accelerators , 1995, Proceedings The International Conference on Application Specific Array Processors.

[13]  P. Ienne,et al.  Implementation of Kohonen's self-organising maps on MANTRA I , 1994, Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems.

[14]  Yuji Sato,et al.  Development of a high-performance general purpose neuro-computer composed of 512 digital neurons , 1993, Proceedings of 1993 International Conference on Neural Networks (IJCNN-93-Nagoya, Japan).

[15]  Dan Hammerstrom.  A Highly Parallel Digital Architecture for Neural Network Emulation , 1991 .

[16]  R. Palmer,et al.  Introduction to the theory of neural computation , 1994, The advanced book program.