Quasi-Static Compact Model for Coupling Between Aligned Contacts on Finite Substrates With Insulating or Conducting Backplanes

We derive a closed-form quasi-static model for the coupling impedance between aligned coplanar rectangular contacts on bulk and epitaxial semiconductor substrates by resolving the 3-D field lines into simpler components (vertical, lateral, fringing, 2-D, etc.). Both insulating and conducting (grounded or floating) backplane conditions are considered. Our model reflects all the geometry and process parameters, and its constants are process independent and universal. The model also gives the capacitive coupling via ambient, i.e., via the region outside the substrate, and specifies conditions under which a given thickness or lateral extension of the substrate can be regarded as infinite. Comparisons with technology computer-aided design simulations and measurements validate the model over a wide range of width/length and width/separation ratios of the contacts.

[1]  Kartikeya Mayaram,et al.  Design-oriented substrate noise coupling macromodels for heavily doped CMOS processes , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[2]  Emre Salman,et al.  Compact substrate models for efficient noise coupling and signal isolation analysis , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[3]  Terri S. Fiez,et al.  A comprehensive geometry-dependent macromodel for substrate noise coupling in heavily doped CMOS processes , 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).

[4]  Robert W. Dutton,et al.  A CAD-oriented modeling approach of frequency-dependent behavior of substrate noise coupling for mixed-signal IC design , 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..

[5]  D. Schroder Semiconductor Material and Device Characterization , 1990 .

[6]  Yiorgos I. Bontzios,et al.  A Unified Method for Calculating Capacitive and Resistive Coupling Exploiting Geometry Constraints on Lightly and Heavily Doped CMOS Processes , 2010, IEEE Transactions on Electron Devices.

[7]  C. C. McAndrew Compact device modeling for circuit simulation , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

[8]  Kaushik Roy,et al.  An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Georges Gielen,et al.  Substrate Noise Coupling in Mixed-Signal ASICs , 2010 .

[10]  Welch,et al.  A simple approach to modeling cross-talk in integrated circuits , 1993 .

[11]  N. P. van der Meijs,et al.  Fast computation of substrate resistances in large circuits , 1996, Proceedings ED&TC European Design and Test Conference.

[12]  William Liu,et al.  MOSFET Models for SPICE Simulation: Including BSIM3v3 and BSIM4 , 2001 .

[13]  R. D. Brooks,et al.  Spreading resistance between constant potential surfaces , 1971 .

[14]  Chichyang Chen,et al.  Electrical characterization and structure investigation of quad flat non-lead package for RFIC applications , 2003 .

[15]  K. Jeppson,et al.  Substrate resistance modeling for noise coupling analysis , 2003, International Conference on Microelectronic Test Structures, 2003..

[16]  Willy Sansen,et al.  analog design essentials , 2011 .

[17]  Kartikeya Mayaram,et al.  A scalable substrate noise coupling model for mixed-signal ICs , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[18]  S. Karmalkar,et al.  Compact Models of Spreading Resistances for Electrical/Thermal Design of Devices and ICs , 2007, IEEE Transactions on Electron Devices.

[19]  Willy Sansen Coupling effects in Mixed analog-digital ICs , 2006 .

[20]  R.W. Dutton,et al.  Synthesized Compact Models and Experimental Verifications for Substrate Noise Coupling in Mixed-Signal ICs , 2006, IEEE Journal of Solid-State Circuits.

[21]  Denis Flandre,et al.  Substrate crosstalk reduction using SOI technology , 1997 .

[22]  T.S. Fiez,et al.  A scalable substrate noise coupling model for design of mixed-signal IC's , 2000, IEEE Journal of Solid-State Circuits.