Design and analysis of an ultra-low-power LC quadrature VCO

This paper presents the design of an ultra-low-power LC quadrature VCO (QVCO). It is designed in a single-poly seven-metal 65-nm CMOS process. Several aspects of state-of-the-art QVCO design are addressed, for example tank design and circuit topologies in nano-meter CMOS technology. To minimize power dissipation, an inductor with a high LQ product of 188 nH at 2.4 GHz, and a self-resonant frequency (fSR) of 3.8 GHz, was designed. According to post-layout simulations, the power dissipation is below 300 μW at a 0.6 V supply. At this supply, the simulated tuning range and phase noise at 1 MHz offset are 10.3% (2.26–2.5 GHz) and −109.6 dBc/Hz respectively. The phase noise figure of merit (FoM) is better than 182.5 dB at all supply voltages of interest, which is competitive to other state-of-the-art QVCOs.

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