On fault probabilities and yield models for VLSI neural networks

We investigate the estimation of fault probabilities and yield for very large scale integration (VLSI) implementations of neural computational models. Our analysis is limited to structures that can be mapped directly onto silicon as truly distributed parallel processing systems. Our work improves on the framework suggested by Feltham and Maly and is also applicable to analog or mixed analog/digital VLSI systems.

[1]  J J Hopfield,et al.  Neural networks and physical systems with emergent collective computational abilities. , 1982, Proceedings of the National Academy of Sciences of the United States of America.

[2]  C Koch,et al.  A two-dimensional analog VLSI circuit for detecting discontinuities in early vision. , 1990, Science.

[3]  C. H. Stapper,et al.  On yield, fault distributions, and clustering of particles , 1986 .

[4]  C.H. Stapper,et al.  Integrated circuit yield statistics , 1983, Proceedings of the IEEE.

[5]  Andreas G. Andreou,et al.  On fault probabilities and yield models for analog VLSI neural networks , 1992, Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.

[6]  Andreas G. Andreou,et al.  A Contrast Sensitive Silicon Retina with Reciprocal Synapses , 1991, NIPS.

[7]  Andreas G. Andreou,et al.  Winner-Takes-All Associative Memory: A Hamming Distance Vector Quantizer , 1997 .

[8]  Kwabena Boahen,et al.  A 48,000 pixel, 590,000 transistor silicon retina in current-mode subthreshold CMOS , 1994, Proceedings of 1994 37th Midwest Symposium on Circuits and Systems.

[9]  A. G. Andreou,et al.  Fault Tolerance in Analog VLSI: Case Study of a Focal Plane Processor , 1990 .

[10]  Andreas G. Andreou,et al.  Storage enhancement techniques for digital memory based, analog computational engines , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[11]  Andreas G. Andreou,et al.  Device mismatch limitations on the performance of an associative memory system , 1993, Proceedings of 36th Midwest Symposium on Circuits and Systems.

[12]  Andreas G. Andreou,et al.  Analog VLSI neuromorphic image acquisition and pre-processing systems , 1995, Neural Networks.

[13]  Duncan M. Walker.  Yield simulation for integrated circuits , 1987 .

[14]  Wojciech Maly,et al.  Physically realistic fault models for analog CMOS neural networks , 1991 .