Cost-Driven Optimization of Coverage of Combined Built-In Self-Test/Automated Test Equipment Testing

As the complexity of design and fabrication for instrumentation-on-silicon systems increases, the optimization of a combined Built-In Self-Test (BIST) and Automated Test Equipment (ATE) process is desirable to meet the high fault coverage while preserving acceptable costs. For digital systems, the costs associated with a combined BIST/ATE testing process mainly consist of the following components: 1) the cost due to the BIST area overhead and 2) the cost due to the overall test time. In general, BIST is faster than ATE, but it can provide only a limited fault coverage; for attaining a higher fault coverage from BIST, additional area (at a corresponding higher cost) is required. However, a higher fault coverage can usually be achieved from ATE, but excessive use of ATE results in additional test time (as an increased cost). The fault coverage of BIST and ATE plays a significant role, because it can affect the area overhead in BIST and the test time in BIST/ATE. This paper proposes a novel numerical method to find the optimized fault coverage by BIST and ATE so that minimal cost can be achieved. The proposed method is then applied to two parallel combined BIST/ATE testing schemes to ensure its validity

[1]  Fabrizio Lombardi,et al.  Analysis and evaluation of multisite testing for VLSI , 2005, IEEE Transactions on Instrumentation and Measurement.

[2]  Christos A. Papachristou,et al.  A built-in self-testing approach for minimizing hardware overhead , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[3]  Brown,et al.  Defect Level as a Function of Fault Coverage , 1981, IEEE Transactions on Computers.

[4]  H. Yasuura,et al.  Analysis and minimization of test time in a combined BIST and external test approach , 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537).

[5]  Prathima Agrawal,et al.  Fault coverage requirement in production testing of LSI circuits , 1982 .

[6]  Nur A. Touba,et al.  Hybrid BIST based on weighted pseudo-random testing: a new test resource partitioning scheme , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[7]  Fabrizio Lombardi,et al.  Test time reduction in a manufacturing environment by combining BIST and ATE , 2002, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

[8]  Charles E. Stroud,et al.  An ASIC level BIST implementation for system level testing , 1991, [1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit.

[9]  Thomas Williams,et al.  Test Length in a Self-Testing Environment , 1985, IEEE Design & Test of Computers.

[10]  Bashir M. Al-Hashimi,et al.  Tackling test trade-offs for BIST RTL data paths: BIST area overhead, test application time and power dissipation , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[11]  Kazumi Hatayama,et al.  Low overhead test point insertion for scan-based BIST , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).