A framework and method for hierarchical test generation
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[1] Peter Muth,et al. A Nine-Valued Circuit Model for Test Generation , 1976, IEEE Transactions on Computers.
[2] Melvin A. Breuer,et al. Diagnosis and Reliable Design of Digital Systems , 1977 .
[3] Hideo Fujiwara,et al. Logic Testing and Design for Testability , 1985 .
[4] M. Ray Mercer,et al. A Topological Search Algorithm for ATPG , 1987, 24th ACM/IEEE Design Automation Conference.
[5] Prabhakar Goel,et al. An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.
[6] Sujit Dey,et al. Corolla based circuit partitioning and resynthesis , 1991, DAC '90.
[7] Melvin A. Breuer,et al. Functional Level Primitives in Test Generation , 1980, IEEE Transactions on Computers.
[8] Füsun Özgüner,et al. 9-V Algorithm for Test Pattern Generation of Combinational Digital Circuits , 1978, IEEE Transactions on Computers.
[9] Hideo Fujiwara,et al. On the Acceleration of Test Generation Algorithms , 1983, IEEE Transactions on Computers.
[10] Wu-Tung Cheng,et al. SPLIT circuit model for test generation , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..
[11] John P. Hayes,et al. Hierarchical test generation using precomputed tests for modules , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[12] Paolo Prinetto,et al. Testing Strategy and Technique for Macro-Based Circuits , 1985, IEEE Transactions on Computers.
[13] John P. Hayes,et al. Hierarchical test generation using precomputed testsd for modules , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.
[14] Janak H. Patel,et al. A Hierarchical Approach to Test Vector Generation , 1987, 24th ACM/IEEE Design Automation Conference.
[15] F. Brglez,et al. Circuit partitioning for logic synthesis , 1991 .
[16] Sheldon B. Akers. A Logic System for Fault Test Generation , 1976, IEEE Transactions on Computers.
[17] Franc Brglez,et al. A framework and method for hierarchical test generation , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.
[18] Jacob A. Abraham,et al. CHIEFS : A Concurrent, Hierarchical and Extensible Fault Simulator , 1985, ITC.
[19] Michael H. Schulz,et al. Hierarchical test pattern generation based on high-level primitives , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.
[20] J. Paul Roth,et al. Diagnosis of automata failures: a calculus and a method , 1966 .
[21] Michael H. Schulz,et al. SOCRATES: a highly efficient automatic test pattern generation system , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[22] L. H. Goldstein,et al. Controllability/observability analysis of digital circuits , 1978 .
[23] David Bryan,et al. Automated synthesis for testability , 1989 .
[24] W. D. Dettloff,et al. A VLSI fuzzy logic inference engine for real-time process control , 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.