Using Novel Configuration Techniques for Accelerated FPGA Aging

In this work we demonstrate a novel method of accelerating FPGA aging by configuring the FPGA to implement thousands of short circuits, resulting in high on-chip currents and temperatures. Three ring oscillators are placed across the chip and are used to characterize the operating frequency of the FPGA fabric. Over the course of several weeks of running the short circuits, with daily characterization of the FPGA performance, we measured a decrease in FPGA frequency greater than 5%. After aging, the FPGA part was repeatedly characterized during a two week idle period. Results indicated that the slowdown did not change, and the aging appeared to be permanent. In addition, we demonstrated that this aging could be induced in a non-uniform manner. In our experiments, the short circuits were all placed in the lower two-thirds of the chip, and one of the characterization ring oscillators was placed at the top of the chip, outside of the region with the short circuits. The fabric at this location exhibited a 1.36% slowdown, only one-quarter the slowdown measured in the targeted region.

[1]  Jonathan M. Smith,et al.  FPGA Viruses , 1999, FPL.

[2]  M. Agostinelli,et al.  Transistor aging and reliability in 14nm tri-gate technology , 2015, 2015 IEEE International Reliability Physics Symposium.

[3]  Rajat Subhra Chakraborty,et al.  Hardware Trojan Insertion by Direct Modification of FPGA Configuration Bitstream , 2013, IEEE Design & Test.

[4]  Mark Mohammad Tehranipoor,et al.  Aging analysis for recycled FPGA detection , 2014, 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

[5]  Jim Tørresen,et al.  Short-Circuits on FPGAs Caused by Partial Runtime Reconfiguration , 2010, 2010 International Conference on Field Programmable Logic and Applications.

[6]  Peter Y. K. Cheung,et al.  Degradation in FPGAs: measurement and modelling , 2010, FPGA '10.

[7]  Stefan Gehrer.  Highly Efficient Implementation of Physical Unclonable Functions on FPGAs , 2017 .

[8]  Chris Lavin,et al.  RapidWright: Enabling Custom Crafted Implementations for FPGAs , 2018, 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

[9]  David Harris,et al.  CMOS VLSI Design: A Circuits and Systems Perspective , 2004 .

[10]  Brad L. Hutchings,et al.  A power side-channel-based digital to analog converterfor Xilinx FPGAs , 2014, FPGA.

[11]  Elaheh Bozorgzadeh,et al.  Aging-aware high-level physical planning for reconfigurable systems , 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

[12]  Abdulazim Amouri,et al.  Aging effects in FPGAs: an experimental analysis , 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

[13]  Patrick Schaumont,et al.  The Impact of Aging on an FPGA-Based Physical Unclonable Function , 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

[14]  Stefan Gehrer,et al.  Aging effects on ring-oscillator-based physical unclonable functions on FPGAs , 2015, 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

[15]  Lirida A. B. Naviner,et al.  Analysis of ageing effects on ARTIX7 XILINX FPGA , 2017, Microelectron. Reliab..