Experimental thermal resistance evaluation of a three-dimensional (3D) chip stack, including the transient measurements

For the thermal management of three-dimensional (3D) chip stack, its thermal resistance needs to be clearly understood. In this study, 3D stacked test chips are fabricated, which are implemented with PN junction diodes for temperature sensors and diffused resistors for heating. At SemiTherm2011, the equivalent thermal conductivity of the interconnection, including BEOL (Back-End-Of-the-Line, wiring layer) is experimentally obtained to be 1.6W/mC and this time, we measure the thermal effect of Cu TSVs and it is experimentally supported that as the Cu TSV area ratio increases, the thermal conductivity of chip with TSVs in the vertical direction increases, on the contrary, that in the horizontal direction decreases. Also, the transient thermal measurement is performed and its result is compared with steady state measurement result. Further, the thermal capacitance measurement of 3D stacked test chip with hot spot heating is performed, which is essential to determine the transient thermal performance of 3D chip stack.

[1]  Mitsumasa Koyanagi,et al.  Future system-on-silicon LSI chips , 1998, IEEE Micro.

[2]  Andreas Ostmann,et al.  3D System Integration Technologies , 2003 .

[3]  E. Beyne,et al.  Steady state and transient thermal analysis of hot spots in 3D stacked ICs using dedicated test chips , 2011, 2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium.

[4]  Peter Ramm,et al.  3D integration technologies for MEMS/IC systems , 2009, 2009 IEEE Bipolar/BiCMOS Circuits and Technology Meeting.

[5]  Katsuyuki Sakuma,et al.  Experimental thermal resistance evaluation of a three-dimensional (3D) chip stack , 2011, 2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium.

[6]  Katsuyuki Sakuma,et al.  Investigations of cooling solutions for three-dimensional (3D) chip stacks , 2010, 2010 26th Annual IEEE Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM).

[7]  W. Marsden.  I and J , 2012 .

[8]  Keiji Matsumoto,et al.  Thermal resistance measurements of interconnections, for the investigation of the thermal resistance of a three-dimensional (3D) chip stack , 2009, 2009 25th Annual IEEE Semiconductor Thermal Measurement and Management Symposium.

[9]  Katsuyuki Sakuma,et al.  3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections , 2008, IBM J. Res. Dev..

[10]  Katsuyuki Sakuma,et al.  Thermal resistance measurements of interconnections for a three-dimensional (3D) chip stack , 2009, 2009 IEEE International Conference on 3D System Integration.