Self-heating effects in gate-all-around silicon nanowire MOSFETs: Modeling and analysis

In this paper, an electro-thermal model is proposed for the first time to accurately investigate the self-heating effects in gate-all-around (GAA) silicon nanowire MOSFETs (SNWTs) for thermal-aware design optimization. The model is derived based on the equivalent thermal network method, in which the impacts of gate length dependence, nanowire diameter dependence and surface roughness on the nanowire channel thermal conductivity as well as the influence of unique GAA structure features on the heat dissipation are taken into account. The proposed model agrees well with the experimental results of SNWTs. Based on the model, the impacts of structure parameters on the current driving capabilities and heat dissipation of SNWTs are discussed. The developed electro-thermal model can be further applied to the thermal-aware design of SNWT-based circuits.

[1]  B. Ryu,et al.  High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[2]  G. Cohen,et al.  High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[3]  O. Faynot,et al.  Novel Si-based nanowire devices: Will they serve ultimate MOSFETs scaling or ultimate hybrid integration? , 2008, 2008 IEEE International Electron Devices Meeting.

[4]  Zhuomin M. Zhang.  Nano/Microscale Heat Transfer , 2007 .

[5]  S.C. Rustagi,et al.  Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance , 2006, 2006 International Electron Devices Meeting.

[6]  William A. Goddard,et al.  Silicon Nanowires as Efficient Thermoelectric Materials. , 2008 .

[7]  Ru Huang,et al.  New Self-Aligned Silicon Nanowire Transistors on Bulk Substrate Fabricated by Epi-Free Compatible CMOS Technology: Process Integration, Experimental Characterization of Carrier Transport and Low Frequency noise , 2007, 2007 IEEE International Electron Devices Meeting.

[8]  Ru Huang,et al.  Experimental study on quasi-ballistic transport in silicon nanowire transistors and the impact of self-heating effects , 2008, 2008 IEEE International Electron Devices Meeting.

[9]  E. Joseph,et al.  Gate-all-around silicon nanowire 25-stage CMOS ring oscillators with diameter down to 3 nm , 2010, 2010 Symposium on VLSI Technology.

[10]  Ru Huang,et al.  Predictive 3-D Modeling of Parasitic Gate Capacitance in Gate-all-Around Cylindrical Silicon Nanowire MOSFETs , 2011, IEEE Transactions on Electron Devices.

[11]  G.D.J. Smit,et al.  Experimental assessment of self-heating in SOI FinFETs , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[12]  Ru Huang,et al.  Investigation on Variability in Metal-Gate Si Nanowire MOSFETs: Analysis of Variation Sources and Experimental Characterization , 2011, IEEE Transactions on Electron Devices.

[13]  K. Endo,et al.  Modeling and Analysis of Self-Heating in FinFET Devices for Improved Circuit and EOS/ESD Performance , 2007, 2007 IEEE International Electron Devices Meeting.

[14]  S. Selberherrb,et al.  A temperature dependent model for the saturation velocity in semiconductor materials , 2022 .

[15]  Soha Hassoun,et al.  Electro-Thermal Analysis of Multi-Fin Devices , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[16]  Rong Tian,et al.  Anomalous heat conduction behavior in thin finite-size silicon nanowires , 2010, Nanotechnology.

[17]  Yiying Wu,et al.  Thermal conductivity of individual silicon nanowires , 2003 .

[18]  A. Majumdar,et al.  Enhanced Thermoelectric Performance of Rough Silicon Nanowires. , 2008 .

[19]  Ru Huang,et al.  Corrections to “Predictive 3-D Modeling of Parasitic Gate Capacitance in Gate-all-Around Cylindrical Silicon Nanowire MOSFETs” [Oct 11 3379-3387] , 2012 .

[20]  C. L. Tien,et al.  Challenges in Microscale Conductive and Radiative Heat Transfer , 1994 .

[21]  Chi On Chui,et al.  Electro-thermal comparison and performance optimization of thin-body SOI and GOI MOSFETs , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[22]  E. H. Sondheimer,et al.  The mean free path of electrons in metals , 2001 .

[23]  B. Ryu,et al.  Gate-All-Around (GAA) Twin Silicon Nanowire MOSFET (TSNWFET) with 15 nm Length Gate and 4 nm Radius Nanowires , 2006, 2006 International Electron Devices Meeting.

[24]  Taku Ohara,et al.  Thermal conductivity of silicon nanowire by nonequilibrium molecular dynamics simulations , 2009 .

[25]  Xi Chen,et al.  Effect of surface roughness on thermal conductivity of silicon nanowires , 2010 .

[26]  S. Phillpot,et al.  Comparison of atomic-level simulation methods for computing thermal conductivity , 2002 .

[27]  E. Pop,et al.  Thermal analysis of ultra-thin body device scaling [SOI and FinFet devices] , 2003, IEEE International Electron Devices Meeting 2003.

[28]  Seri Lee,et al.  cONSTRICTION/SPREADING RESISTANCE MODEL FOR ELECTRONICS PACKAGING , 1996 .

[29]  E. Pop,et al.  Impact of phonon-surface roughness scattering on thermal conductivity of thin si nanowires. , 2009, Physical review letters.