Thermal and mechanical design and analysis of 3D IC interposer with double-sided active chips

In this investigation, the thermal and mechanical design and analysis of a TSV (through-silicon via) interposer which supports 2 active chips on its top-side and 1 active chip on its bottom-side (a real 3D IC integration with an interposer) are studied. Emphasis is placed on the thermal design and analysis of the chips' average temperatures and the applied cooling capability on the heat spreader/sink. To simplify the simulations, an equivalent model, that can preciously determine the thermal performances of TSVs and solder bumps/balls, is introduced instead of a complicate detail 3D model. Another emphasis is placed on the determination of the creep strain energy density per cycle of the solder bumps/balls between the chips and the TSV interposer, the TSV interposer and the organic package substrate, and the package substrate and the PCB (printed circuit board) under environmental thermal cycling condition.

[1]  K. Saban Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity , Bandwidth , and Power Efficiency , 2009 .

[2]  G. Mori,et al.  Through-silicon-via technology for 3D integration , 2010, 2010 IEEE International Memory Workshop.

[3]  John H. Lau,et al.  Process integration of 3D Si interposer with double-sided active chip attachments , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

[4]  Kevin Cai,et al.  3D Si Interposer Design and Electrical Performance Study , 2013 .

[5]  Sheng-Tsai Wu,et al.  Ultra low-cost through-silicon holes (TSHs) interposers for 3D IC integration SiPs , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[6]  Sheng-Tsai Wu,et al.  Thermal Performance of 3D IC Integration with Through-Silicon Via (TSV) , 2011 .

[8]  Heng-Chieh Chien,et al.  Thermal evaluation and analyses of 3D IC integration SiP with TSVs for network system applications , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[9]  L. Madden,et al.  Quality and Reliability of 3D High-Performance Heterogeneous Integration through Die Stacking , 2012 .

[10]  B. Banijamali,et al.  Outstanding and innovative reliability study of 3D TSV interposer and fine pitch solder micro-bumps , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[11]  B. Banijamali,et al.  Advanced reliability study of TSV interposers and interconnects for the 28nm technology FPGA , 2011, Electronic Components and Technology Conference.

[12]  M. Brillhart,et al.  Addressing bandwidth challenges in next generation high performance network systems with 3D IC integration , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[13]  R. Chaware,et al.  Assembly and reliability challenges in 3D integration of 28nm FPGA die on a large high density 65nm passive interposer , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.