Weryfikacja modelowa hierarchicznej specyfikacji sterownika logicznego
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[1] Iwona Grobelna,et al. Diagramy aktywności języka UML i sieci Petriego w systemach sterowania binarnego - od transformacji do weryfikacji , 2010 .
[2] Thomas Kropf. Introduction to Formal Hardware Verification: Methods and Tools for Designing Correct Circuits and Systems , 1999 .
[3] Iwona Grobelna,et al. Diagramy aktywności UML w projektowaniu rekonfigurowalnych sterowników logicznych , 2012 .
[4] M. Adamski,et al. Hierarchical UML activity diagrams into control interpreted petri nets transformation , 2012, Proceedings of the 19th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2012.
[5] Iwona Grobelna,et al. Formal verification of embedded logic controller specification with computer deduction in temporal logic , 2011 .
[6] Marian Adamski,et al. Hardware behavioural modelling, verification and synthesis with UML 2.x activity diagrams , 2012, PDeS.
[7] Marian Adamski,et al. Petri nets and Activity Diagrams in logic controller specification - transformation and verification , 2010, Proceedings of the 17th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2010.
[8] E. Allen Emerson,et al. The Beginning of Model Checking: A Personal Perspective , 2008, 25 Years of Model Checking.