Impact of TSV induced thermo-mechanical stress on semiconductor device performance

Evaluation of the impact caused by Through-Silicon Vias (TSV) induced thermo-mechanical stress on device performance is becoming important due to the close proximity between TSVs and the semiconductor devices in 3D integration. From the literatures, there exist discrepancies between theory, simulated and experimental results presented. For accurate predictions, we simulated stress build-up by taking the full CMOS process flow into consideration. We considered the interaction between TSV, stressors such as tensile stress liner and Shallow Trench Isolation (STI) and device channel. From the results, it was found that the nMOSFET Ion variation is less than 2% at Keep Out Zone (KOZ) of 1 μm due to TSV induced stress while the Ion variation is about 30% due to the tensile stress liner. Hence, the impact of TSV induced stress on nMOSFET performance is insignificant compared to that of tensile stress liner in the device.

[1]  Suk-kyu Ryu,et al.  Thermo-mechanical reliability of 3-D ICs containing through silicon vias , 2009, 2009 59th Electronic Components and Technology Conference.

[2]  J. West,et al.  Practical implications of via-middle Cu TSV-induced stress in a 28nm CMOS technology for Wide-IO logic-memory interconnect , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[3]  Suk-kyu Ryu,et al.  Effect of Thermal Stresses on Carrier Mobility and Keep-Out Zone Around Through-Silicon Vias for 3-D Integration , 2012, IEEE Transactions on Device and Materials Reliability.

[4]  J. Cluzel,et al.  Investigation on TSV impact on 65nm CMOS devices and circuits , 2010, 2010 International Electron Devices Meeting.

[5]  P. Soussan,et al.  Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance , 2010, 2010 International Electron Devices Meeting.

[6]  M. Koyanagi.  3D integration technology and reliability , 2011, 2011 International Reliability Physics Symposium.

[7]  K.F. Yang,et al.  TSV process optimization for reduced device impact on 28nm CMOS , 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

[8]  Sung Kyu Lim,et al.  TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC , 2012, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Yeong L. Park,et al.  Impact of TSV proximity on 45nm CMOS devices in wafer level , 2011, 2011 IEEE International Interconnect Technology Conference.

[10]  Li Yu,et al.  Methodology for analysis of TSV stress induced transistor variation and circuit performance , 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

[11]  H. Y. Li,et al.  Development of Wafer-Level Warpage and Stress Modeling Methodology and Its Application in Process Optimization for TSV Wafers , 2012, IEEE Transactions on Components, Packaging and Manufacturing Technology.