6 An Optimized Code Generation Approach for Complex Instruction Set PDSPs

A programmable digital signal processor (PDSP) is a special-purpose microprocessor with specialized architecture and instruction set for implementing DSP algorithms. Typical architectural features include multiple memory partitions (onchip, off-chip, data memory, program memory, etc.), multiple (generally pipelined) arithmetic and logic units (ALUs), nonuniform register sets, and extensive hardware numeric support [1,2]. Single-chip PDSPs have become increasingly popular for real-time DSP applications [3,4]. The newest introductions from several manufacturers offer peak computing power approaching that of supercomputer systems of only a few years ago. However, to fully utilize the available computing power, the software designer must face the difficult task of programming in low-level assembly language. High-level languages (HLLs) are attractive to software designers because they simplify the task of programming. Unlike assembly language, HLL programs are readable, maintainable, and portable to other processors. All of these features contribute to increase productivity and reduce development cost. An HLL compiler translates the instructions present in an HLL program into assembly instructions, more easily understood by the processor. Commercially available HLL compilers for PDSPs have existed for many years [5]. Unfortunately, the performance of those compilers is still acceptable only to a few noncritical applications. The reason is twofold. First, the majority of those com-