The increasing demand for high-bandwidth interconnection between integrated circuits requires large numbers of I/Os per chip as well as high data rates per I/O. Key limitations in meeting these requirements include channel characteristics and I/O power consumption. Even in short interconnects, the channel attenuation at very high data rates is significant, and using receiver equalization can greatly improve the link performance [1–5]. However, compensating a high level of loss requires many taps of equalization, which can significantly reduce the power efficiency of the link. Parallel data transmission increases the aggregate data rate, but compact traces placed in close proximity suffer from a high level of crosstalk interference. This problem is exacerbated when transmit pre-emphasis techniques are exploited to boost the high frequency gain. While the use of differential signaling can mitigate the effect of crosstalk, it requires twisting pairs leading to area and bandwidth penalties.
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