Design guidelines to achieve minimum energy operation for ultra low voltage tunneling FET logic circuits

A tunneling field effect transistor (TFET) attracts attention, because TFET circuits can achieve better energy efficiency than conventional MOSFET circuits. Although design issues in ultra low voltage logic circuits, such as the minimum operatable voltage (VDDmin), have been investigated for MOSFET's, VDDmin for TFET's have not been discussed. In this paper, VDDmin of TFET logic circuits is evaluated for the first time and a closed-form expression of VDDmin is derived, which indicates that the within-die threshold voltage variation (σVT) strongly affects VDDmin. In addition, since it is not clear how much the energy of the logic circuits is quantitatively reduced when both the subthreshold swing (S) and the power supply voltage are reduced, an analytical equation of the minimum energy of TFET logic circuits is also derived. From the derived equations, the design guideline is presented for the device engineers of TFET's that σVT should be reduced as S decreases.