Manufacturability and robust design of nanoelectronic logic circuits based on resonant tunnelling diodes

The manufacturability of logic circuits based on quantum tunnelling devices, namely double-barrier resonant tunnelling diodes (RTD), is studied in detail. The homogeneity and reproducibility of III/V mesa technology-based devices is experimentally evaluated and interpreted using multiple I-V characteristic simulations. The experimental sensitivity of the RTD I-V parameters on well and barrier thickness is compared with multiple I-V simulations. With shrinking minimum feature size the fluctuations in the peak current can be directly attributed to an RTD area variation caused by the increasing impact of lithography and etching on lateral dimensions. These results prove that the III/V technology fulfils the requirements for a large scale integration of RTD devices. A nanoelectronic circuit architecture based on an improved MOBILE threshold logic gate is presented. Detailed SPICE simulations using the experimental data show that clock and supply voltage fluctuations are tolerated up to ± 0.1 V at a supply voltage of 0.7 V. Very strong local peak voltage variations of 15 per cent in opposite directions would be necessary to have a critical impact on to the circuit functionality. Smaller deviations only affect the timing without degrading the reliability of the circuit. Consequently, the design of a stable power supply and clocking scheme is more important for the overall circuit performance than the small relative deviations of the RTD peak voltage.

[1]  Clifton G. Fonstad,et al.  Pseudomorphic In0.53Ga0.47As/AlAs/InAs resonant tunneling diodes with peak‐to‐valley current ratios of 30 at room temperature , 1988 .

[2]  J.P.A. van der Wagt,et al.  RTD/HFET low standby power SRAM gain cell , 1998, IEEE Electron Device Letters.

[3]  S. Selberherr,et al.  Physical models for strained and relaxed GaInAs alloys: Band structure and low-field transport , 1997 .

[4]  U. Auer,et al.  A novel 3-D integrated RTD-HFET frequency multiplier , 1997, Conference Proceedings. 1997 International Conference on Indium Phosphide and Related Materials.

[5]  Werner Prost,et al.  HR XRD for the analysis of ultrathin centrosymmetric strained DB-RTD heterostructures , 1998 .

[6]  C. Ohler,et al.  Heterojunction band offsets and Schottky-barrier heights: Tersoff’s theory in the presence of strain , 1998 .

[7]  K. Maezawa,et al.  InP-based high-performance monostable-bistable transition logic elements (MOBILEs) using integrated multiple-input resonant-tunneling devices , 1996, IEEE Electron Device Letters.

[8]  Pinaki Mazumder,et al.  Digital circuit applications of resonant tunneling devices , 1998, Proc. IEEE.

[9]  Werner Prost,et al.  Threshold logic circuit design of parallel adders using resonant tunneling devices , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[10]  Wim Magnus,et al.  Accurate modelling of the accumulation region of a double barrier resonant tunnelling diode , 1996 .

[11]  U. Auer,et al.  A novel 3-D integrated HFET/RTD frequency multiplier , 1996 .

[12]  Shawn Patrick Stapleton,et al.  Sequential tunneling versus resonant tunneling in a double‐barrier diode , 1993 .

[13]  T.C.L.G. Sollner,et al.  New self-aligned planar resonant-tunneling diodes for monolithic circuits , 1997, IEEE Electron Device Letters.

[14]  V. A. Wilkinson,et al.  Tunnel devices are not yet manufacturable , 1997 .

[15]  Michael P. Hasselbeck,et al.  Electron-electron interactions in the nonparabolic conduction band of narrow-gap semiconductors , 1998 .

[16]  Peter Glösekötter,et al.  Resonant tunneling transistors for threshold logic circuit applications , 1999, Proceedings Ninth Great Lakes Symposium on VLSI.