Statistical modeling for efficient parametric yield estimation of MOS VLSI circuits

Large statistical variations are often found in the performance of VLSI circuits; as a result, only a fraction of the circuits manufactured may meet performance goals. Interdie variations in length and width, oxide capitance, and flat band voltage are shown to be responsible for process induced variations in circuit performance. This statistical model is the basis for SPYE, Statistical Parametric Yield Estimator. A linear approximation for the yield body is used to obtain an accurate and efficient prediction of parametric yield. SPYE requires five to seven simulations for yield estimation, only slightly more than are needed for conventional "worst case analysis." Defect or particle related yield are not addressed.

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