A High Optical Performance 2.8μm BSI LOFIC Pixel with 120ke FWC and 160μV/e Conversion Gain

In this paper, we report about a prototype CMOS image sensor with a 2.8m back side illuminated (BSI) pixel that employs the lateral overflow integration capacitor (LOFIC) to further expand dynamic range of our reported sensors. Full well capacity of 120ke and conversion gain of 160V/e have been achieved. For high optical performance with the BSI structure, an n-layer of the deep photodiode under LOFIC is formed. Owing to this structure, 70% peak quantum efficiency and 91% angular response at ±20 have been achieved without blooming. INTRODUCTION Achieving both high sensitivity and high dynamic range (DR) is required for many imaging applications, especially for security/surveillance applications. Recently, over 85dB single exposure high dynamic range (SEHDR) CMOS image sensors (CIS) with high full well capacity (FWC) photodiode (PD) were reported. However, it is difficult to drastically increase the PD FWC further. Thus, one of solutions for over 90dB SEHDR is LOFIC technology. In the LOFIC CIS, the floating diffusion (FD) capacitor (CFD) and the LOFIC can be designed independently by only adding the LOFIC and a switch between FD and LOFIC. As a result, high sensitivity by minimized CFD and high FWC by maximized LOFIC have been achieved at the same time. This advantageous characteristic resolves the trade-off between high FWC and high sensitivity that surely exists in the conventional CISs. However, the conventional LOFIC pixel still has a disadvantage that is low optical performance compared to the typical 4Tr. pixel because the optical fill factor of the PD is lower due to the area occupation by the LOFIC. In this paper, a prototype chip of a new LOFIC pixel built in BSI process technology to improve optical performance is presented. CONCEPT AND OPERATION Fig. 1 (a), (b) and (c) show a circuit schematic, a timing diagram and potential diagram of the LOFIC pixel, respectively. Compared with conventional 4Tr. pixels, there are an additional switch (SG) and the LOFIC (CS). To achieve high FWC, the LOFIC pixel accumulates all the overflow photoelectrons from PD during exposure in CS until signal is read out. At the first stage of readout, the reset and signal levels are read out in a high gain mode (HCG). Then, the photoelectrons in the PD and FD/CS are mixed and the mixed signal is read out in a low gain/high FWC mode (LCG). By using the HCG signals for low illuminance conditions and the LCG signals for high illuminance, expanding DR is realized. Fig. 2 (a) shows a cross sectional view of a conventional front side illuminated (FSI) LOFIC pixel. Increasing PD fill factor is limited by the large CS in a pixel. On the other hand, in our proposed structure using the BSI technology (Fig. 2 (b)), there is a deep n-layer under the CS for the following three purposes; (i)To increase fill factor for high optical performance, (ii)To expand the PD area for high FWC in HCG, (iii)To reduce the neutral region under the CS for crosstalk suppression. Also, the deep n-layer is laid out in a square shape to obtain optical symmetry. To collect all the photoelectrons generated in the BSI side, we designed the dopant concentration of the deep n-layer lower than that of the n-layer of the FSI side and formed concentration gradient in the deep n-layer to generate electric field towards FSI side. In addition, an n-layer under the transfer gate (TG) and the SG gate is formed to obtain the overflow path from PD to CS and to prevent blooming. The potential barrier at the overflow path is designed lower than that of the pixel-to-pixel isolation. Also, to remove leakage currents that are generated at shallow trench isolation (STI) and the gate oxide surface, PN junction isolation around FD instead of STI, and buried overflow path under the TG and the SG are introduced. EVALUATION RESULTS Fig. 3 shows photoelectric conversion characteristics of this prototype chip. Two curves exhibit good linearity. We obtained 160V/e conversion gain (C.G.) and 7ke FWC in HCG, and 120ke FWC in LCG. Compared to our previous devices, we have achieved to increase LCG FWC without reduction of HCG C.G.. Because signal electrons at the conjunction point of HCG and LCG signals are 6ke, which is near the HCG saturation, we have achieved 38dB signal to noise ratio at that point. Fig. 4 and Fig. 5 show the measured results of quantum efficiency (Q.E.) and angular response (AR), respectively. Although the microlens structure of this prototype chip is not fully optimized, 70% peak Q.E. and 91% AR at ±20 have been achieved. These values are comparable to those of our previous sensors. In addition, Q.E. in LCG matches that of HCG, which suggests that all the overflow photoelectrons from PD are transferred to FD and CS without blooming due to the overflow path. Fig. 6 (a) and (b) show the measured results of Gr/Gb ratio. Under the blue light condition, less than 2% deviation has been achieved and this suggests that more than 98% photoelectrons generated in the BSI side under the CS are collected in the FD without crosstalk. Fig. 7 shows HDR sample images captured by this prototype chip. We captured some color objects which are illuminated by the halogen light or miniature light. Even for the scene of 100dB differences in brightness and darkness, this prototype chip captured all the color objects without halation. CONCLUSION A prototype chip with a BSI LOFIC pixel has been demonstrated. Fig. 8 and Table 1 show a chip micrograph and a performance comparison, respectively. We have achieved 120ke FWC and 160μV/e C.G. with the smallest non-shared LOFIC pixel. Through optimization of microlens structure, we expect over 70% peak Q.E. and over 91% AR at ±20 without blooming will be achieved. Also, assuming the same column signal chain of our previous sensors , read noise of less than 1e and over 100dB DR will be obtained. These techniques are readily available for new SEHDR CIS’s for security and IoT cameras. ACKNOWLEGMENT The authors gratefully acknowledge the support by Yutaka Sato in acquiring HDR images. REFERENCES [1] I. Takayanagi, et al., “An 87dB single exposure dynamic range CMOS image sensor with a 3.0μm triple conversion gain pixel,” Proc. IISW, pp.274-277, 2017 [2] I. Takayanagi, et al., “An over 90 dB intra-scene single-exposure dynamic range CMOS image sensor using a 3.0 μm triple-gain pixel fabricated in a standard BSI process,” Sensors, 18, 203, 2018 [3] K. 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